Lab 1 Examining Architecture of GHRD - ArrowElectronics/arrow-soc-workshops GitHub Wiki

Module Objective

In this module you will review the architecture of the design that will be created in Platform Designer. You will also examine the layout of the SoCKit. Developing software for an Intel PSG SoC requires an understanding of the design flow of the Platform Designer system integration tool. Typically, a design starts with system requirements. These system requirements become inputs to the system definition. System definition is the first step for implementation in the design flow process.

System Architecture

There are many components on the SoCKit that can be used, including the LCD, flash, Audio DACs, and IR receiver.
The system that we will finish creating in Platform Designer is built by using a standard library of re-useable IP blocks. The orange section of this diagram is the HPS section, while the green section is the FPGA section. The HPS section was configured in the HPS component in Platform Designer. There are three bridges between the HPS and FPGA sections. You will focus on the LWHPS2FPGA bridge connected peripherals for this lab, specifically the LED PIO. The LED PIO is mapped through the bridge into the HPS addressable map.

Examine the System Tool Flow

The diagram above depicts the typical flow for an SoC design. Platform Designer and Quartus Prime generate the following sets of files:

• A set of XML files are created that define the system description. These XML files are utilized by the ARM DS-5 software tool to create a project for the software application. You can find the files here:

• Platform Designer also generates the HDL files (Verilog or VHDL) for the defined system. These HDL files are then used by Quartus Prime to compile and generate a set of files that defines the hardware system. This set of files includes the HDL files, Tcl (Tool Command Language) files that define dedicated pin locations for selected HPS peripherals, Tcl files that define the Multiport Memory Controller in the HPS & FPGA, QIP files that include selected IP and SDC (Synopsis Design Constraint files) utilized by TimeQuest to constrain the complete system design.

• Quartus Prime will then generate a simple SOF (SRAM Object File) image that is used to configure the FPGA.

Examine Arrow's Cyclone V SoCKit

Examine the components on the Cyclone V SoC board hardware:

Block Diagram of the SoCKit

There are many components included on the SoCKit, including the LCD, flash, Audio DACs, and IR receiver.
A block diagram of the board: