Lab 2 Create Quartus Project - ArrowElectronics/arrow-soc-workshops GitHub Wiki

In this section, you will open a Quartus Prime project that contains the Platform Designer system. In addition, you will specify I/O constraints and settings for this design by executing a Tcl script.

Launch Quartus Prime Project

• Launch the Quartus Prime v19.1 software: Select -> All Programs -> Intel PSG 19.1.0.211 Lite Edition -> Quartus Prime Lite Edition 19.1.0.211 -> Quartus Prime 19.1
• A splash screen will appear, select Open Project:

• Browse to the directory: C:\Intel\Sockit\SoCKit_HW_Lab_19.1 and select soc_system.qpf and then select Open.

You can also use the File menu to open the project:

• Select File -> Open Project and browse to the directory: C:\Intel PSG_trn\SoCKIT_Materials_19.1\SoCKit\SoCKit_HW_lab_19.1.
• Select soc_system.qpf.
• The Quartus Prime project will open. The project already contains a top level Verilog file (..\top\ghrd_top.v) and a Platform Designer project (soc_system.Platform Designer) that will be modified in the following modules.
• Please take a look at the top level file. To do this, double click on the ghrd_top icon in the Project navigator Window or (select: File -> Open and browse to the ..\top directory and open ghrd_top.v)

• The ghrd_top.v contains all of the I/O for the HPS instance as well as all the FPGA I/O. In addition, you will find the instance for the Platform Designer component, soc_system at the end of the file.

Your Quartus Prime project is set up. You are ready to start building your Platform Designer system.