Lab 3 Platform Designer - ArrowElectronics/arrow-soc-workshops GitHub Wiki

Launch Platform Designer

From the Tools menu, select the Platform Designer icon .

There may be a slight delay while the Platform Designer application launches.

Open the File named soc_system.qsys.

There will be various components that are already included in the Platform Designer system, while others will need to be built.

Build the Platform Designer System

The first component that you will verify and change is the HPS (Hard Processor System).

Verify the Hard Processor System

The Hard Processor System (HPS) consists of the dual ARM Cortex A9 with various peripherals enabled. The following is a block diagram of some of the entities available in the HPS.

Configure the HPS

• In the Platform Designer window, right-click on the hps_0 component and choose Edit...

• We will now configure the HPS with the correct pin multiplexing for the peripherals to accommodate the interfaces on the SoCKit. This process will also include configuring the clocks, the Multiport Memory Controller, the three high speed ports: HPS to the FPGA, FPGA to HPS and FPGA to Multiport Memory Controller and various other settings. For complete details please refer to the Cyclone V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual.

Please note that there are multiple tabs for: FPGA Interfaces, Peripheral Pins, HPS Clocks and under the **SDRAM **tab there are sub-tabs that are used to configure the HPS, as shown here.

Configure the FPGA Interfaces for the HPS

Under the FPGA Interfaces tab, there are various options in the General, AXI Bridges, FPGA to HPS SDRAM, Resets, DMA Peripheral Request, and **Interrupts **sections.
In the General section, verify that the following options are all disabled (unchecked) as shown.

• Enable MPU standby and event signals
• Enable general purpose signals
• Enable Debug APB interface
• Enable FPGA Cross Trigger Interface
• Enable FPGA Trace Port Interface Unit
• Enable FPGA Trace Port Alternate FPGA Interface
• Enable boot from fpga signals
• Enable HGPLI Interface

Verify that only the Enable System Trace Macrocell Hardware events option is enabled as shown in the figure below.

Explanation of options:

• Enable MPU standby and event signals - Enables signals used to indicate if the microprocessor is in standby mode to the FPGA and can wake up an MPCore processor from a Wait For Event (WFE) state.
• Enable general purpose signals - Enables a pair of 32-bit unidirectional general purpose interfaces between the FPGA and the FPGA Manager in the HPS.
  • The FPGA Manager is used to configure the FPGA, mimics passive parallel 32-bit configuration, Partial Reconfiguration, Compressed FPGA configuration images, AES encrypted configuration images, monitors the configuration-related signals, provides 32 general purpose inputs and outputs to the FPGA.
• Debug APB interface - Enables debug interface to the FPGA, allowing access to debug components in the HPS.
• Enable System Trace Macrocell hardware events - Enables System Trace Macrocell (STM) hardware events, allowing logic inside the FPGA to insert messages into the trace stream.
• Enable FPGA Cross Trigger Interface - Enables the cross trigger interface (CTI), which allows trigger sources and sinks to interface with the embedded cross trigger (ECT).
• Enable FPGA Trace Port Interface Unit - Enables an interface between the trace port interface unit (TPIU) and logic in the FPGA. The TPIU is a bridge between on-chip trace sources and a trace port.
• Enable boot from FPGA ready - Enables an input to the HPS indicating whether a preloader is available in on-chip RAM. If the input is asserted, a preloader image is ready at memory location 0.
• Enable boot from FPGA on failure - Enables an input to the HPS indicating whether a fallback preloader is available in on-chip RAM. If the input is asserted, a fallback preloader image is ready at memory location 0. The fallback preloader is to be used only if the HPS boot ROM does not find a valid preloader image in the selected flash memory device.
• Enable HLGPI Interface - This will instantiate 14 general purpose DDR inputs. If you check these signals will be available in the HPS IO conduit in Platform Designer and are at same IO voltage as the DDR interface. Please refer to the Pin Connection Guidelines.

In the AXI Bridge section, ensure that both the FPGA-to-HPS interface width is set to 64-bit and HPS-to-FPGA interface width is set to 64-bit. Both of these interfaces can be set to 32, 64, 128-bits, or Unused.

• Enabling the FPGA to HPS interface allows masters within the FPGA to access to HPS peripherals.
• Enabling the HPS to FPGA interfaces allows HPS masters to access the FPGA peripherals.

Verify that the Lightweight HPS-to-FPGA interface width is set to 32 bit. A 32 bit AXI interface optimized for low latency is thus enabled.

After making these changes, the HPS should now look like this:

Scrolling down the FPGA interface tab, there are more options. There are sections for the FPGA-to-HPS SDRAM Interface, **Resets **and DMA Peripheral Request.

Verify the FPGA to HPS SDRAM Interface section has one entry: f2h_sdram0.

• This enables the FPGA to gain access to the HPS SDRAM subsystem from the FPGA fabric. This particular FPGA to HPS interface provides up to six ports to the HPS’s multiport SDRAM controller. The bus interface provided to the FPGA can be AXI-3 or Avalon Memory Mapped.

Ensure that the Enable FPGA-to-HPS debug reset request, Enable FPGA-to-HPS warm reset request, and Enable FPGA-to-HPS cold reset request options are all enabled. There are several options and the Reset Manager is very sophisticated. Therefore, please refer to the Cyclone V Device Handbook Volume 3: Hard Processor System Reference Manual: Section I, Chapter 3 for details on the Reset Manager.

Explanation of reset options (Do NOT implement these changes):

• Enable HPS-to-FPGA cold reset output - Enable interface for HPS-to-FPGA cold reset output
• Enable HPS warm reset handshake signals - Enable an additional pair of reset handshake signals allowing soft logic to notify the HPS when it is safe to initiate a warm reset in the FPGA fabric.
• Enable FPGA-to-HPS debug reset request - Enable interface for FPGA-to-HPS debug reset request
• Enable FPGA-to-HPS warm reset request - Enable interface for FPGA-to-HPS warm reset request
• Enable FPGA-to-HPS cold reset request - Enable interface for FPGA-to-HPS cold reset request

Verify the DMA peripheral request is set to the **default **of **No **for each of the eight channels. The designer can enable each direct memory access (DMA) controller peripheral request ID individually. Each request ID enables an interface for FPGA soft logic to request one of eight logical DMA channels to the FPGA.

Ensure that the Enable FPGA-to-HPS interrupts is **enabled **. This enables interrupt signals from the FPGA to the MPU in the HPS.

The HPS-to-FPGA interrupts should all be disabled as shown in Figure 4.2.1.4. An interrupt signal can be provided to the FPGA for each one of the peripherals that are included in this section.

4.2.2 Configure HPS Peripheral Pin Multiplexing (MAC, NAND, QSPI, SDIO, USB) Under the Peripheral Pins tab, there are options to enable the HPS peripherals. The peripherals in the HPS are available to as many as three sets of HPS I/O pins. A Peripherals Mux Table is available at the bottom of this tab to make it a simpler and more intuitive task for the designer. Also, please note that all HPS peripherals are available for pin out via the FPGAs pins. If you put your cursor over a particular peripheral’s mode icon: a list of the signal to pin for a particular I/O set per pin is displayed in a pop-up box, as shown in Figure 4.2.2.1.

 <img src="https://github.com/ArrowElectronics/arrow-soc-workshops/blob/master/hardware_lab/Lab3_9.jpg" width="500"/>  

To see a pin multiplexing error, change the EMAC0 pin multiplexing default of Unused to HPS I/O Set 0, as shown in Figure 4.2.2.2 and 4.2.2.3.

These errors occur since each peripheral available on the HPS go to at least one set of HPS I/O. The multiplexing for each I/O Set is controlled by selecting the specific HPS peripheral's I/O Set. When the EMAC pin multiplexing was selected, the pins for several of the other peripherals had already used these I/O pins, resulting in a conflict. Please note that all pins that are not utilized by an HPS peripheral can be enabled as a General Purpose I/O Pin. Conflicts (column and row are in Red/Burgundy):

No Conflicts: (For the peripheral selected mux_select column is green):

Change the EMAC0 pin multiplexing back to Unused to remove the errors. The selected pins need to match the Cyclone V SoC board to avoid any errors. Verify that the Platform Designer settings match the following screenshots to enable the Ethernet MAC, QSPI Flash Controller, SDMMC, USB Controller, SPI Controllers, Uart Controllers, and I2C Controllers.

 <img src="https://github.com/ArrowElectronics/arrow-soc-workshops/blob/master/hardware_lab/Lab3_15.jpg" width="500"/>  

There should be no errors and the conflict setting should look as follows:

  <img src="https://github.com/ArrowElectronics/arrow-soc-workshops/blob/master/hardware_lab/Lab3_19a.jpg" width="500"/>  

The PLL reference clocks between the HPS and FPGA are NOT enabled for this lab. Therefore, your screenshot should be as shown below:

None of the HPS Peripherals were selected to be available in the FPGA; therefore, none of these clocks are Peripheral FPGA Clocks:

then the result in the HPS Clocks tab would be:

If you made the change to SPIM1 pin multiplexing change it back to UNUSED now!

4.2.3.2 Configuring HPS Output Clocks (Output Clocks is NEW in Version 14.0)

4.2.3.2.1 HPS Output Clocks: Clock Sources Please leave the settings to the default:

The bullets below are descriptive. Do NOT implement these changes. Explanation of user clock options for the Output tab: - Peripheral PLL reference clock source: This selects the reference clock for the HPS peripherals and can be set to the: EOSC1 Clock, EOSC2 Clock, FPGA-to-HPS peripheral reference clock. EOSC1 & EOSC2 are based upon the frequency at the HPS I/O pins: HPS_CLK1 and HPS_CLK2, D25 and F25 for the Cyclone V SX 5CSXFC6D6F31C6. The FPGA-to-HPS peripheral reference clock is set under the Input tab. Please refer to Figure 4.2.3.7. - SDMMC clock source – Sets the clock source for the Secure Digital/Multimedia Card controller FPGA-to-HPS peripheral reference clock – f2h_periph_ref_clk as defined in the input Clock tab Main NAND SDMMC Clock – Selects the PLL output from the “Main Clock Group” MPU, L3 & L4 & Debug PLL C4 from the HPS Clock Manager Peripheral NAND SDMMC Clock – Selects the PLL output from the “Peripheral Clock Group” Peripheral PLL C3 from the HPS Clock Manager Please refer to Figure 4.2.3.8. - NAND clock source – Sets the clock source for the NAND Flash controller FPGA-to-HPS peripheral reference clock – f2h_periph_ref_clk as defined in the input Clock tab Main NAND SDMMC Clock – Selects the PLL output from the “Main Clock Group” MPU, L3 & L4 & Debug PLL C4 from the HPS Clock Manager Peripheral NAND SDMMC Clock – Selects the PLL output from the “Peripheral Clock Group” Peripheral PLL C3 from the HPS Clock Manager Please refer to Figure 4.2.3.9. - QSPI clock source – Sets the clock source for the QSPI controller FPGA-to-HPS peripheral reference clock – f2h_periph_ref_clk as defined in the input Clock tab Main QSPI Clock – Selects the PLL output from the “Main Clock Group” MPU, L3 & L4 & Debug PLL C3 from the HPS Clock Manager Peripheral QSPI Clock – Selects the PLL output from the “Peripheral Clock Group” Peripheral PLL C2 from the HPS Clock Manager Please refer to Figure 4.2.3.10. - L4MP clock source – L4 Master Peripheral Clock: l4_mp_clk Main Clock – Selects the PLL output from the “Main Clock Group” main_base_clk or C1 from the Main PLL Peripheral base clock – Selects the PLL output from the “Peripheral Clock Group” from the Peripheral PLL C4 - L4SP clock source – L4 Slave Peripheral Clock: l4_sp_clk Main clock - Selects the PLL output from the “Main Clock Group” main_base_clk or C1 from the Main PLL Peripheral base clock – Selects the PLL output from the “Peripheral Clock Group” from the Peripheral PLL C4

4.2.3.2.2 HPS Output Clocks: Main PLL Output Clocks – Desired Frequencies The ESOC1 clock frequency and ESOC2 clock frequency External Clock Sources drive the HPS Clock manager PLLs (Main Clock Group, Peripheral Clock Group, SDRAM Clock Group & OSC1 Clock Group PLLs).

Please leave the settings :

The bullets below are descriptive. Do NOT implement these changes. - MPU clock frequency – Sets the clock frequency for the processor must be unchecked to configure with own frequency - L3MP clock frequency – L3 Master Peripheral clock frequency: l3_mp_clk Divides by 1 or 2 the PLL output from the main_base_clk or C1 from the Main PLL - L3SP clock source – L3 Slave Peripheral Clock: l3_sp_clk Can be divided by 1 or 2 the L3PM clock (l3_mp_clk) - Debug AT clock frequency – Debug AT Clock: dgb_at_clk Derived from the Main PLL: C2 output and can be divided by 1 or 2 - Debug Timer clock frequency – Debug Timer Clock: dgb_timer_clk Derived from the Main PLL: C2 output - Debug clock frequency – Debug Clock: dgb_clk Originates from dbg_at_clk divided by 2 or 4, derived from the Main PLL: C2 output - Debug trace clock frequency – Debug trace clock: dgb_trace_clk Originates from dbg_base_clk divided by 1, 2, 4, 8 or 16, derived from the Main PLL: C2 output - L4 MP clock frequency – L4 Main Peripheral clock: l4_mp_clk Originates from dbg_base_clk or periph_base_clk divided by 1, 2, 4, 8 or 16 - L4 SP clock frequency – L4 Slave Peripheral clock: l4_sp_clk Originates from dbg_base_clk or periph_base_clk divided by 1, 2, 4, 8 or 16 - Configuration HPS-to-FPGA user 0 clock frequency – h2f_user0_clock Originates from cfg_h2f_user0_base_clk which is the Main PLL: C5 output

4.2.3.2.3 HPS Output Clocks: Peripheral Output Clocks – Desired Frequencies Please leave the settings:

• SDMMC clock frequency – Originates from the Peripheral PLL: C3 output: periph_nand_sdmmc_base_clk
  • NAND clock frequency – Originates from the Peripheral PLL: C3 output: periph_nand_sdmmc_base_clk
  • QSPI clock frequency – Originates from the Peripheral PLL: C3 output: periph_qspi_base_clk
  • EMAC0 clock frequency – emac0_base_clk Originates from the Peripheral PLL, C0 output: emac1_base_clk
  • EMAC 1clock frequency – emac1_base_clk Originates from the Peripheral PLL, C1 output: emac1_base_clk
  • USB clock frequency – usb_mp_clk Originates from the Peripheral PLL, C4 output: periph_base_clk Can be divided by 1,2,4,6, or 16
  • SPI clock frequency – spi_m_clk Originates from the Peripheral PLL, C4 output: periph_base_clk Can be divided by 1,2,4,6, or 16
  • CAN0 clock frequency – can0_clk Originates from the Peripheral PLL, C4 output: periph_base_clk Can be divided by 1,2,4,6, or 16
  • CAN1 clock frequency – can1_clk Originates from the Peripheral PLL, C4 output: periph_base_clk Can be divided by 1,2,4,6, or 16
  • GPIO clock frequency – Originates from the Peripheral PLL, C4 output: periph_base_clk Divided by 24

4.2.3.2.4 HPS Output Clocks: HPS-to-FPGA user clocks Please leave the default settings:

• Enable HPS-to-FPGA user 0 clock – h2f_user0_clock Originates from cfg_h2f_user0_base_clk which is the Main PLL: C5 output Refer to Figure 4.2.3.12
  • Enable HPS-to-FPGA user 1 clock Originates from h2f_user1_base_clk which is the Peripheral PLL: C5 output Refer to Figure 4.2.3.14
  • Enable HPS-to-FPGA user 2 clock Originates from h2f_user0_base_clk which is the SDRAM PLL: C5 output Refer to Figure 4.2.4.2

4.2.4 Configure SDRAM (The HPS External Memory Interface) Please note that Intel PSG has an 8 hour class available for Implementing, Simulating, and Debugging External Memory Interfaces and this resource should be utilized for an in depth understanding of EMIFs.
Under the SDRAM tab, there are options to set the SDRAM parameters for the HPS External Memory Interface. The SoCKit has two Micron 1.35V DDR3L SDRAM devices connected to the HPS (256Mb x 16 x 2 = 1GB at 1.5V vs. 1.35v). There are four tabs for the SDRAM configuration: PHY Settings, Memory Parameters, Memory Timing, and Board Settings. Select the PHY Settings tab. The Clocks and Advanced PHY Settings are required.
Change the memory clock frequency to 400.0 MHz (as shown in Figure 4.2.4.1). This is the rate for the Micron memory devices. Verify that the supply voltage is set to be 1.5V V DDR3. The 1.35 V variation of this Micron device is used; but the Vdd/Vddq are connected to 1.5v in order to reduce the system power supply complexity for SoCKit. The settings should now look like:

Select the Memory Parameters tab (as shown in Figure 4.2.4.4). The settings are needed to match the DDR3 device. A table from the Micron datasheet shows the row address, bank address and column address. The Micron memory used on this board has the parameters in the last column (256 Meg x 16).

The datasheet also shows that the DM and DQS# pins are enabled.

Verify the parameters that are selected as shown below:

The Memory Initialization Options are at the bottom of this page, where the values are again taken from the Micron datasheet.

Under the Memory Timing tab, timing parameters need to be verified:

The memory timings listed above match those in the datasheet.

Under the Board Settings tab: Verify that in the Setup and Hold Derating section, the option is set to Use Intel PSG's default settings. Verify that in the Channel Signal Integrity section, the option is set to Use Intel PSG's default settings.

Since the board design is complete, the board skews (which are linked to timing differences between traces) are known. These settings should be set to:

At the top of the Arria V/Cyclone V Hard Processor System Parameters Window, close the window by selecting the X or by clicking the Finish button, as the settings for the Hard Processor System are now configured.

In the export column associated with the HPS_0, there are five signals that need to be exported to the top level of the project. This is the reason why there are five signals already associated as shown in Figure 4.2.4.9 below.

• Set the Width to be 4, which is the number of LEDs on the board connected to the FPGA I/O pins.
• Ensure that the direction is set to Output.
• Select Finish (as shown in Figure 4.2.5.2)

Change the default name of the PIO component to be led_pio.

• To change the name, select the component (click to highlight), right click, and select Rename.

Since the LED connections will be driven by the FPGA I/O, the LED signals will need to be exported to the top level of the project. To do so:

• Double click in the export column associated with the external connection of the led_pio and the following should automatically show up: led_pio_external_connection. If not, then type: led_pio_external_connection

The component should now look like:

• Set the width to be 4. Ensure that the direction is set to Input.
• Set the Edge capture register to Synchronously capture on the FALLING edge.
• Enable Generate IRQ. Set the IRQ Type to EDGE.
• Refer to Figure 4.2.6.2 before proceeding to check your settings
  • Select Finish

The settings for the component should now look like:

Figure 4.2.6.2 Save the Platform Designer system, select: File -> Save. After saving the file, there will be errors which will be resolved in the next step. Review other Platform Designer components There are many other components in the Platform Designer system that have already been configured for the SoCKit embedded system. Therefore, these components do not need to be configured. A summary of these components: The FPGA array provides on chip memory blocks that can be used to build up internal RAM (or ROM) blocks of memory that is available for any master in the Platform Designer system. This provides the HPS Cortex-A9 MPU access to very low-latency, high speed memory for code or variable storage. This is the onchip_memory2_0 component. The JTAG to Avalon Master accepts encoded streams of bytes of transaction data on the JTAG interface and initiates Avalon-MM (Memory-Mapped) transactions on the Avalon-MM interface. The JTAG-to-Avalon Master is also used for debugging, with tools such as System Console and SignalTap. Both System Console and SignalTap will be used later in this workshop.
The System ID peripheral is a very important peripheral to include in your system. It allows the software development tools to validate that the software application is being built for the correct hardware system. Basically, it will not allow software to be executed on an incompatible hardware configuration. The SoCKit has four DIP switches on it that are connected to the FPGA I/O pins. The dipsw_pio is an input PIO peripheral that is used to read in the DIP Switch settings in a fashion similar to the button_pio peripheral. Software developers need to have access to a debug serial port from the target to leverage printf debugging, input control commands, log status information, etc. The jtag_uart peripheral connects to the debugger console and provides an interface to the developer’s console for that and other purposes. Interrupts are signals that need immediate attention. Interrupts have higher priority than other processes. The interrupt_capturer component is an Avalon Memory Mapped module (written in Verilog) to capture system interrupts and pass them on to the HPS Cortex-A9 MPU.

4.3 System Configuration 4.3.1 Connect HPS interfaces to FPGA Peripherals The Platform Designer components that were just created (led_pio and button_pio) have not been connected; therefore, there are errors. These errors will be removed in the next steps.

The following steps will connect the components to the system. These include the Avalon Memory Mapped signals as well as the clock and reset signals. There are two methods that can be utilized to connect your new system components: visually by using the patch panel to connect the nodes or busses (dots), or by right clicking on the menu (as described below).
To connect the led_pio to the system via the menu method: right click on the clk signal of the led_pio. The available connections are connected as shown:

• Select clk_0.clk

The clock of the PIO is now connected to the 100 MHz clock from the FPGA’s dedicated clock input pin AF14. The following connections will be made with the same process of right clicking on the signal and then selecting the signal to be connected. The following table describes what signals are to be connected together. Name of Component Name of Signal What component that the signal is to be connected to What signal of the component that is to be connected to led_pio clk clk_0 clk led_pio reset clk_0 clk_reset led_pio s1 fpga_only_master master led_pio s1 mm_bridge_0 m0 button_pio clk clk_0 clk button_pio reset clk_0 clk_reset button_pio s1 fpga_only_master master button_pio s1 mm_bridge_0 m0

Table 4.3.1.1 As the connections are made, the errors at the bottom of the Platform Designer window will be removed. Since the IRQs have yet to be set, there will still be errors and they will be removed in the next section.
4.3.2 Set IRQs Components with interrupts can be set to have higher priority than other system components; therefore, the interrupts in our Platform Designer system need to be assigned.
The DIP switch, button and JTAG all have interrupts that will be captured by the interrupt capture module. These interrupts will be connected to the HPS component. The dipsw_pio and jtag_uart components already have their interrupts assigned.
The pio_button component also needs to have an IRQ assigned to it.
To assign IRQ, first the push button needs to be connected to the IRQs and then the interrupts level needs to be assigned. - Right click on the irq of the button_pio so that the button_pio irq can be selected, as seen in the following screenshot.

• Select the hps0.f2h_irq0 so that this interrupt is selected.
  • Repeat this step again, but now select the intr_capturer_0.interrupt_receiver.
    The interrupts should now look like this:

Next, verify the interrupt level for the push button. - Scroll to the right to view the IRQ column in Platform Designer, where the level of the IRQ will be assigned.

• Click in the boxes and type in the number 1.

Errors still remain at the bottom of the Platform Designer screen and these will be removed in the following steps. 4.3.3 Set Base Addresses The system has a memory map. A system’s memory map consists of addresses that are assigned to a component and these address ranges cannot overlap. The addresses can be assigned automatically or manually. For this workshop, the addresses are assigned manually since the software portion of this workshop will use these specific addresses.

To assign base addresses: - Select the Address Map tab in Platform Designer, as shown above in Figure 4.3.3.1. This is a table that includes all of the memory -mapped slaves in the design and the address range that each connected memory-mapped master uses to address that slave. The blank cells indicate that there is no connection between that master and slave. To change the address range, double-click on the current range in the cell. - Change the led_pio.s1 to 0x0001_0040 for both fpga_only_master and mm_bridge_0 - Change the button_pio.s1 to 0x0001_00c0 for both fpga_only_master and mm_bridge_0

Now, the "Address Map" tab is seen as:

Now all of the errors in your Platform Designer system should be eliminated! Once these values are entered, go back to the System Contents tab and go the led_pio and select the row associated with the base addresses, as shown below. In the Base address column, select the lock icon by the Base Address, so that the Base Address is locked, as seen below. Locking an address prevents a base address from being changed.

Repeat the same step for button_pio so that its address range is also locked. 4.3.4 Set AXI Bridge to Secure The system has three JTAG to Avalon Master bridges and in Module 5 we want to allow System Console the ability to write to the HPS memory space from the FPGA. Specifically, to the HPS GPIO’s (GPIO53, GPIO54, GPIO55 & GPIO56) associated with the LEDs on pins A24, G21, C24 and E23. In order for the system to allow this capability, the hps_only_master.master port must be set to secure. In Platform Designer, select and right mouse click on the Connections column and a drop down dialog box will appear as shown in Figure 4.3.4.1

Check “Show Security Column”.

The “Security” column will now be visible in Platform Designer:

Select the master under “hps_only_master” and click on “Non-secure” and change to “Secure”:

• Save the Platform Designer system, with File -> Save. 4.3.5 Block Diagram of the Golden Hardware Reference Design The Golden Hardware Reference Design (GHRD) is an important part of the Golden Software Reference Design (GSRD) and consists of the following components:

  • ARM Cortex™-A9 MPCore HPS
  • Four user push-button inputs
  • Four user DIP switch inputs
  • Four user I/O for LED outputs
  • 64KB of on-chip memory
  • JTAG-to-Avalon master bridges
  • Interrupt capturer for use with System Console
  • System ID

4.3.5.1 MPU Address Map This section presents the address maps as seen from the MPU (Cortex-A9) side. HPS-to-FPGA Address Map The memory map of soft IP peripherals, as viewed by the microprocessor unit (MPU), starts at HPS-to-FPGA address offset 0xC000_0000. The following table lists the offset of each peripheral in the FPGA portion of the SoC.

Peripheral Address Offset Size (bytes) Attribute onchip_memory2_0 0x0 64K On-chip RAM as scratch pad

Table 4.3.5.1 Lightweight HPS-to-FPGA Address Map The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is listed in the following table. Peripheral Address Offset Size (bytes) Attribute sysid_Platform Designer 0x1_0000 8 Unique System ID led_pio 0x1_0040 8 LED output display dipsw_pio 0x1_0080 8 DIP Switch Input button_pio 0x1_00c0 8 Push button Input jtag_uart 0x2_0000 8 JTAG UART console

Table 4.3.5.2 4.3.5.2 JTAG Master Address Map There are two JTAG master interfaces in the design, one for accessing non-secure peripherals in the FPGA fabric, and another for accessing secure peripherals in the HPS through the FPGA-to-HPS Interface. The following table lists the address of each peripheral in the FPGA portion of the SoC, as seen through the non-secure JTAG master interface. Peripheral Address Offset Size (bytes) Attribute sysid_Platform Designer 0x0001_0000 8 Unique System ID led_pio 0x0001_0040 8 4 LED outputs dipsw_pio 0x0001_0080 8 4 DIP Switch inputs button_pio 0x0001_00c0 8 4 push button inputs jtag_uart 0x0001_0000 8 JTAG UART console onchip_memory2_0 0x0000_0000 64K On-chip RAM

Table 4.3.5.3 4.3.5.3 Interrupt Routing The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface. Peripheral Interrupt Number Attribute dipsw_pio f2h_irq0[0] 4 DIP Switch Inputs button_pio f2h_irq0[1] 4 Push Button Inputs jtag_uart f2h_irq0[2] JTAG UART

Table 4.3.5.4

The interrupt sources are also connected to an interrupt capturer module in the system, which enables System Console to be aware of the interrupt status of each peripheral in the FPGA portion of the SoC. 4.4 Generate the System Please Double-check to make sure that all the component names, clocks and base addresses in your Platform Designer system match the names below.

First half of the Platform Designer Window:

Second half of the Platform Designer window:

• From the menu bar, select Generate and then select Generate HDL… from the drop down menu.
  • From the Generation window that pops up, accept the defaults and click the Generate button.
  • If it asks you to save, select Yes.

The Generate process will take several minutes. You will receive the following warnings, but they can be disregarded. Click Close.

Exit Platform Designer by clicking File then Exit and then Save when it asks if you would like to save the system.

A simulation model for the System wasn’t created; therefore, you will not find the */simulation/soc_system.sip file.

Platform Designer will generate the HDL files (Verilog or VHDL) for the defined system. These HDL files are then used by Quartus Prime to compile and generate a set of files that defines the hardware system. This set of files includes the HDL files, Tcl (Tool Command Language) files that define dedicated pin locations for selected HPS peripherals, Tcl files that define the Multiport Memory Controller in the HPS & FPGA, QIP files that include selected IP and SDC (Synopsis Design Constraint) files utilized by TimeQuest to constrain the complete system design, and SIP files that include the Simulation IP files required to complete a simulation. Both the QIP and SIP files use Tcl syntax.

In Quartus Prime, you can find these files by selecting File -> Open, then go to the soc_system/synthesis directory (select All Files(.)) for all of the files to be displayed.

CONGRATULATIONS!!

You have just built your first Platform Designer system!