x32_mult - dspsandbox/Canvas GitHub Wiki
images/DSP-modules/x32_mult.png
Description
MULTIPLY arithmetic with clear logic. In order to preserve a 32 bit depth, the multiplication output correspond to bits 62 down to 31 of the 64 bit wide bare multiplication. Hence, out=(in0*in1)/2^31 and the absolute gain of the multiplication is smaller than 1. This limitation is overcome by sending the output to a x32_shiftL module.
Please note that this core requires 4 of the 80 DSP slices available on your Redpitaya. If possible, consider substituting the multiplication with a suitable bit shift (see x32_shiftL and x32_shiftR).
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in0 | Rx | 32 bit | |
| in1 | Rx | 32 bit | |
| clr | Rx | 1 bit | |
| out | Tx | 32 bit | out=(in0*in1)/2^31 IF clr=0 out=0 IF clr=1 |
Pipeline latency (clk @ 125 MHz)
6 clk cycles.