x32_shiftR - dspsandbox/Canvas GitHub Wiki
images/DSP-modules/x32_shiftR.png
Description
SHIFT RIGHT arithmetic.
Ports
| Name | Direction | Width | Comment |
|---|---|---|---|
| in0 | Rx | 32 bit | |
| shiftR | Rx | 32 bit | Min: 0 Max: 31 |
| out | Tx | 32 bit | out=(in>>shiftR) |
Pipeline latency (clk @ 125 MHz)
1 clk cycle.