x32_shiftL - dspsandbox/Canvas GitHub Wiki

images/DSP-modules/x32_shiftL.png

Description

SHIFT LEFT arithmetic.

Ports

Name Direction Width Comment
in0 Rx 32 bit
shiftL Rx 32 bit Min: 0 Max: 31
out Tx 32 bit out=(in<<shiftL)

Pipeline latency (clk @ 125 MHz)

1 clk cycle.

VHDL

x32_shiftL.vhd