XPS_Block_Class_Fields - david-macmahon/wiki_convert_test GitHub Wiki
simulink_name
string simulink_name
simulink_name is a string indicating the full hierarchical name of the block in the Simulink design.
The value of field is automatically set by the xps_block class constructor. Overriding this field in a child class can have unexpected consequences.
parent
string parent
parent is a string indicating the full hierarchical name of the block's parent block in the Simulink design.
The value of field is automatically set by the xps_block class constructor. Overriding this field in a child class can have unexpected consequences.
xsg_obj
xps_block xsg_obj
xsg_obj is an xps_xsg-class (a child class of the xps_block class) object associated with the XSG Core Config yellow block in the Simulink design.
The value of field is automatically set by the xps_block class constructor. Overriding this field in a child class can have unexpected consequences.
type
string type
type is a string indicating the value of the yellow block's tag field.
The value of field is automatically set by the xps_block class constructor. Overriding this field in a child class can have unexpected consequences.
type should correspond to the name of the child class associated with a yellow block.
ip_name
string ip_name
ip_name is a string that specifies the name of the associated EDK pcore to copy from the pcore repository and instantiate in the design.
ip_version
string ip_version
ip_version is a string that specifies the version of the associated EDK pcore to copy from the pcore repository and instantiate in the design.
ip_version should have the EDK pcore X.YY.Z revision format; i.e., 1.00.a, 2.01.b, etc.
supp_ip_names
cell supp_ip_names
supp_ip_names is a cell array of strings that specifies the names of supplemental EDK pcores to copy from the pcore repository.
If supp_ip_names is non-empty but the first element of the cell array is an empty string, that indicates that the pcore referenced by the class's ip_name and ip_version will be added to the list of pcores to be copied from the pcore repository. Otherwise, the pcore indicated in the first element of the cell array will be used instead.
Each entry in supp_ip_names should have a corresponding entry in supp_ip_versions.
supp_ip_versions
cell supp_ip_versions
supp_ip_versions is a cell array of strings that specifies the versions of the supplemental EDK pcores to copy from the pcore repository.
Each string in the cell array should use the EDK pcore X.YY.Z revision format; i.e., 1.00.a, 2.01.b, etc.
Each entry in sup_ip_versions should correspond to an entry in supp_ip_names.
opb_address_offset
double opb_address_offset
opb_address_offset is a Matlab double with an integer value specifying the memory space, in bytes, allocated to this pcore on the OPB bus.
A non-zero value in this field indicates that this pcore needs a bus attachment to a OPB bus.
plb_address_offset
double plb_address_offset
plb_address_offset is a Matlab double with an integer value specifying the memory space, in bytes, allocated to this pcore on the PLB bus.
A non-zero value in this field indicates that this pcore needs a bus attachment to a PLB bus.
opb_address_align
double opb_address_align
opb_address_align is a Matlab double with an integer value specifying the OPB bus address alignment.
A non-zero value in this field indicates that the start address of the allocated memory space must be an integer multiple of the alignment value.
plb_address_align
double plb_address_align
plb_address_align is a Matlab double with an integer value specifying the PLB bus address alignment.
A non-zero value in this field indicates that the start address of the allocated memory space must be an integer multiple of the alignment value.
ports
struct ports
ports is a structure of cell arrays that defines ports for the pcore that are connected to the Simulink design via Xilinx Gateway In/Out Blocks.
The value of field is automatically set by the xps_block class constructor. Overriding this field in a child class can have unexpected consequences.
Each field in the structure defines an MHS port entry named field_name in the interface's pcore instantiation. Each field consists of a 3-element cell array {a b c} where:
- a = a Matlab decimal number indicating the port bitwidth
- b = a Matlab string in or out indicating the port directionality
- c = a Matlab string with the name of the net to be connected to the port of the pcore
ext_ports
struct ext_ports
ext_ports is a structure of cell arrays that defines the IP’s external ports in the EDK project. These are the ports of the pcore that are external at the top level; that is, they must be connected to the IOBs in the FPGA (global ports in the MHS).
Each field in the structure will create an MHS port entry connected to the field_name port of the pcore. Each field should consist of a 7-element cell array {a b c d e f g} where:
- a = a Matlab decimal number indicating the port bitwidth
- b = a Matlab string in or out indicating the port directionality
- c = a Matlab string with the name of the net and external port to be connected to the port of the pcore
- d = a Matlab-evaluable string that can access the structures in BEE2_hw_routes.mat mapping each bit of the port to an IOB pin number
- e = a Matlab string vector=true or vector=false indicating whether the port is a single bit or a vector (allows for 1-bit vectors)
- f = a Matlab structure of pairs of Matlab strings that correspond to MHS constraints
- g = a Matlab structure of pairs of Matlab strings that correspond to UCF constraints
For example, the following entry in a class constructor:
ext_ports.data_in_p = {4 'in' 'adc0_data_in_p' '{ROACH.zdok0_p{[1 3 5 7],:}}' 'vector=true' struct() struct('IOSTANDARD', 'LVDS_25', 'DIFF_TERM', 'TRUE')}
would indicate a connection to the 4-bit port of the pcore named data_in_p. It would be connected via net adc0_data_in_p to the MHS port adc0_data_in_p. Each bit in the vector would receive a LOC constraint according to the ROACH.zdok0_p structure stored in BEE2_hw_routes.mat and an IOSTANDARD constraint of LVDS_25 and a DIFF_TERM constraint of TRUE.
More specifically, one would expect to see the following lines in the system.mhs of the project:
(beginning of pcore instantiation)
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PORT data_in_p = adc0_data_in_p
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(end of pcore instantiation)
PORT adc0_data_in_p = adc0_data_in_p, DIR = 'in', VEC = [3:0]
and the following lines in the system.ucf of the project:
NET "adc0_data_in_p<0>" LOC = M31 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;
NET "adc0_data_in_p<1>" LOC = M25 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;
NET "adc0_data_in_p<2>" LOC = K24 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;
NET "adc0_data_in_p<3>" LOC = H28 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE ;
misc_ports
struct misc_ports
misc_ports is a structure of cell arrays that defines ports for the pcore that are connected to other instantiated pcores. These do not connect to the Simulink design, and are not external ports.
Each field in the structure will create an MHS port entry named field_name in the interface's pcore instantiation. Each field should consist of a 3-element cell array {a b c} where:
- a = a Matlab decimal number indicating the port bitwidth
- b = a Matlab string in or out indicating the port directionality
- c = a Matlab string with the name of the net to be connected to the port of the pcore
For example, the following entry in a class constructor:
misc_ports.app_clk_in = {1 'in' 'sys_clk'}
would indicate a connection to the 1-bit port of the pcore named app_clk_in to the net sys_clk.
More specifically, one would expect to see the following lines in the system.mhs of the project:
(beginning of pcore instantiation)
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PORT app_clk_in = sys_clk
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(end of pcore instantiation)
buses
struct buses
'''buses ''' is a structure of structures of cell arrays that specifies bus connections to the Simulink design. Each field in the structure represents a number of ports in the Simulink design that are grouped as a bus to the interface pcore.
Each field in the structure will create an MHS bus_interface entry named field_name in the interface's pcore instantiation connected to a bus_interface in the Simulink designs's pcore instantiation. It is also used in the pcore generation for the Simulink design, specifying ports in the MPD as belonging to a bus.
Each structure should be a structure of 2 additional fields busif and ports detailing the connectivity of the bus interface:
- bus_if should a a 1x1 cell array with a string specifying the name of the bus to be connected to both bus_interface entries.
- ports should be a cell array of strings defining the port connections on the bus.
For example, the following entry in a class constructor:
buses.CMD_BUS.busif = {'test_design_CMD_BUS'};
buses.CMD_BUS.ports = {};
buses.CMD_BUS.ports = [buses.CMD_BUS.ports, 'Cmd_Bus_Addr'];
buses.CMD_BUS.ports = [buses.CMD_BUS.ports, 'Cmd_Bus_WrEn'];
buses.CMD_BUS.ports = [buses.CMD_BUS.ports, 'Cmd_Bus_RdEn'];
buses.CMD_BUS.ports = [buses.CMD_BUS.ports, 'Cmd_Bus_Data'];
buses.CMD_BUS.ports = [buses.CMD_BUS.ports, 'Cmd_Bus_Valid'];
specifies that on this interface pcore related to this class there is a bus_interface named CMD_BUS with ports Cmd_Bus_Addr, Cmd_Bus_WrEn, Cmd_Bus_RdEn, Cmd_Bus_Data, and Cmd_Bus_Valid. In the MHS instantiation of the pcore, the CMD_BUS bus_interface entry will be connected to the bus named test_design_CMD_BUS to the Simulink design pcore instantiation's bus_interface entry of test_design_CMD_BUS.
More specifically, one would expect the following lines in the system.mhs of the project:
(beginning of Simulink design pcore instantiation)
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BUS_INTERFACE test_design_CMD_BUS = test_design_CMD_BUS
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(end of Simulink design pcore instantiation)
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(beginning of interface pcore instantiation)
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BUS_INTERFACE CMD_BUS = test_design_CMD_BUS
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(end of interface pcore instantiation)
The bus_interface connection of the Simulink design pcore MHS entry will take the place of the declaration of each individual port on the bus.
In addition, the MPD file of the Simulink design pcore would show that certain ports as being a part of the bus:
(beginning of Simulink design pcore MPD)
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BUS_INTERFACE BUS = _CMD_BUS, BUS_STD = TRANSPARENT, BUS_TYPE = UNDEF
Cmd_Bus_Addr = Cmd_Bus_Addr, BUS = test_design_CMD_BUS, DIR = out, VEC = [15:0]
Cmd_Bus_WrEn = Cmd_Bus_WrEn, BUS = test_design_CMD_BUS, DIR = out
Cmd_Bus_RdEn = Cmd_Bus_RdEn, BUS = test_design_CMD_BUS, DIR = out
Cmd_Bus_Data = Cmd_Bus_Data, BUS = test_design_CMD_BUS, DIR = inout, VEC = [31:0]
Cmd_Bus_Valid = Cmd_Bus_Valid, BUS = test_design_CMD_BUS, DIR = in
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(end of Simulink design pcore MPD)
Note that the port directionality and bitwidth are still set by the ports field of the object.
interfaces
struct interfaces
interfaces is a structure of strings that defines bus interfaces for the pcore that are connected to other instantiated pcores. These interfaces do not connect to the Simulink design.
Each field in the structure defines an MHS bus_interface named
field_name in the interface's pcore instantiation. Each field
should have a string value defining the bus name that the bus
interface should be connected to.
For example, the following entry in a class constructor:
interfaces.CONF_BUS = 'conf_bus_0';
specifies that on this interface pcore related to this class there is a bus_interface named CONF_BUS. In the MHS instantiation of the pcore, the CONF_BUS bus_interface entry will be connected to the bus named conf_bus_0.
parameters
struct parameters
parameters is a structure of strings or Matlab doubles that specify parameters to be passed to the instantiated pcore.
Each field in the structure specifies an MHS parameter named field_name in the interface's pcore instantiation.