PCIE CXL - MarekBykowski/readme Wiki

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CXL (Express Compute Link) HW validation

Integrate and validate CXL protocol in a sumulated env. with Synopsys VCS and Virtual Platform (SIMICs).

PCI/PCIe

  • Basics: [1], [2], and [3]
  • PCIe enumaration, bus-device-function, PCIe controller, bridge, endpoints: [4], and [5]
  • From Linux kernel and device tree:
    • What PCIe host driver reads from device tree [6]
    • Accessing PCIe Config Regs on [7]
  • Compiled a doc on "Single Root Enumeration Example" [8]

Express Compute Link

  • Spec revision 2.0 [9]

SIMICs

  • Run SIMICs tutorial for the Simics Quick-Start Platform (QSP), extended with a custom Mandelbrot accelerator PCI-express (PCIe) add-in card in [10].

    First install SIMICs. SIMICs is provided by Intel in a public release [11] and sold commercially by Wind River. Intel's free-of-charge version supports only Intel Architecture. Follow the User Guide [12] and open Documentation through cd ~/simics-projects/my-simics-project-1/; ./documentation &. The PCIe system the tutorial is about looks as in the fig. below:

align=center

  • Read through the Documentation (opened in the bullet point above):
    • Model Builder's User Guide
    • Device Modeling Language 1.4 Reference Manual
    • API Reference Manual

Synopsys VCS simulator [13]

An interesting similarity is an Aglilex FPGA-Silicon system from Intel (former Altera) with Coherent Processor Attach with Compute Express Link (CXL) (on the very left hand side in the Fig. below)

align=center

It enables creation or use of an FPGA-based accelerator sittin on the R-tile, which is incorporated in selected members of the Intel® Agilex™ I-series and Intel® Agilex™ M-series FPGA families [14]. As an option it also enables VCS simulation for protocol compliance.

References

[1] http://xillybus.com/tutorials/pci-express-tlp-pcie-primer-tutorial-guide-1
[2] PCI_Express_Basics_Background
[3] PCIE bridge in device tree
[4] https://www.khoury.northeastern.edu/~pjd/cs7680/homework/pci-enumeration.html
[5] https://wiki.osdev.org/PCI
[6] https://elinux.org/Device_Tree_Usage#PCI_Host_Bridge
[7] IA Accessing PCI Express Configuration Registers Using Intel Chipsets
[8] Single Root Enumeration Example
[9] CXL spec
[10] w02-builder-workshop-instructions.pdf
[11] https://www.intel.com/content/www/us/en/developer/articles/guide/simics-simulator-installation.html
[12] https://www.intel.com/content/www/us/en/developer/articles/guide/simics-simulator-get-started.html
[13] http://cc.ee.ntu.edu.tw/~ric/teaching/SoC_Verification/S06/Homework/HW1/vcs.pdf
[14] https://www.intel.co.uk/content/www/uk/en/products/details/fpga/intellectual-property/interface-protocols/cxl-ip.html