Netfpga 10g openflow switch - wvoice/Accelerators GitHub Wiki

Name

openflowswitch

Location

contrib-projects/openflowswitch

Design Document

See the design document for the full documentation, including the installation.

Installation

Carefully follow the installation part (Section 6 and 7) of the design document.

Software

You may find the OpenFlow agent from here. Again, make sure you read the Section 7 of the design document before checking out the code.

IP Cores

• Project Specific cores
  • openfllow_datapath
• NetFPGA-10G Specific cores
  • nf10_10g_interface
  • nf10_mdio
  • DMA
  • nf10_bram_output_queues
  • nf10_input_arbiter
• Xilinx AXI Peripheral
  • axi_interconnect
  • axi_uartlite
  • axi_timebase_wdt
• Microblaze Subsystem
  • MicroBlaze
  • lmb_v10
  • lmb_bram_if_cntlr
  • bram_block
  • proc_sys_reset
  • clock_generator
• Other
  • diff_input_buf

Description

This is a hardware portion of OpenFlow1.0 Switch on NetFPGA-10G. The main role of the hardware portion is to modify packet header fields and forward it from one port to another/other port(s) at a line rate, with referring to flow tables residing in hardware. For overall view including its associated software, see the attached design document.

Block Diagram