Dma engine - wvoice/Accelerators GitHub Wiki

Name

DMA

Version

v1.00a

v1.10a new!

Author

Mario Flajslik (mariof_at_stanford.edu)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/contrib/pcores/dma_v1_00_a

Interface Types

PCIe, AXI4-Stream, AXI

Busses

M_AXIS: Master AXI4-Stream (RX) bus, 64bit

S_AXIS: Slave AXI4-Stream (TX) bus, 64bit

M_AXI: Master AXI4-LITE bus, 32bit address, 32 bit data

S_AXI: Slave AXI4-LITE bus, 32 bit address, 32 bit data

Parameters

C_BASEADDR: Base address for the S_AXI interface

C_HIGHADDR: High address for the S_AXI interface

Register map

There are 8 AXI registers (32 bit) implemented for test purposes. One can write any data into them and then read it out later. They do not affect the operation of the DMA in any way. These registers are located at: C_BASEADDR...C_BASEADDR+7

Description

This module serves as a DMA engine for the reference NIC design. It includes Xilinx' PCIe core and AXI4-LITE master module (see references 2 and 3). To the other NetFPGA modules it exposes AXIS (master+slave) interfaces for sending/receiving packets, as well as a AXI4-LITE master interface through which all AXI registers can be accessed from the host (over PCIe). There is also included a set of AXI registers that can be connected via the AXI4-LITE slave bus to the same AXI interconnect for testing purposes (these registers can be removed at a later time, but at the time of the development of this module there were no other suitable AXI registers to test the AXI master functionality).

As there is only one AXIS set of interfaces, the module uses T_USER signal to multiplex between all four ports as defined in the NetFPGA standard IP interfaces documentation.

SystemVerilog source code for the module is provided for reference purposes. Should one want to make changes to the module a new netlist will need to be generated by a tool that supports SystemVerilog and is capable of exporting an edif file.

Changing the frequency

This core is shipped with two different frequency mode: 125MHz (Default) and 250MHz. Users may choose appropriate mode to balance throughput and timing requirements. To switch mode, follow the steps below (changing 125MHz core to 250MHz)

  1. Point the symbolic link to the new EDIF. From pcore's top level directory
cd netlist
rm dma_engine.edf
ln -s dma_engine_250MHz.edf dma_engine.edf
  1. Modify the XCO From pcore's top level directory
cd xco
nano endpoint_blk_plus_v1_15.xco

Change the line

CSET interface_freq=125

To

CSET interface_freq=250_default
  1. Remake the core From pcore's top level directory
make

External references

  1. AXI Spec: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.amba/index.html

  2. Xilinx PCIe: pcie_blk_plus_ug341.pdf

  3. Xilinx AXI4-LITE master: ds836_axi_master_lite.pdf