EXR Processor Family - tiredboffin/fffw GitHub Wiki
CPU
The SoCs used in many Fujifilm cameras between 2010 and 2015 can generally be grouped under the "EXR Processor" series. While these processors developed more powerful image processing capabilities (DSP) over time, they retained the same CPU architecture. This makes them quite similar from a reverse-engineering perspective.
The processors in the proposed group are:
| Processor Name | CPU | SoC Marking |
|---|---|---|
| EXR Processor | Dual(?) ARM Cortex-R4F | FF4224 |
| EXR Processor Pro | Dual ARM Cortex-R4F | FF4224, co-processor FF4226 |
| EXR Processor II | Dual Cortex-R4F r1p4 | FF4227 |
EXR (FF4224)
The FF4224 processor includes ARM Cortex-R4 Core (see Does-XF1-have-dual-CPU?)
Note: the HS30EXR schematic diagram indicates the presence of a single ARM1136J-S CPU, which appears to be a copy-paste error. This discrepancy could point to broader issues with the reliability of the schematic.
Co-processor
The FF4226 module was initially introduced in the X-Pro1. It might be entirely unrelated, but this was also the first camera to feature an X-Trans sensor.
Based on the below snippet from the X-Pro1 schematic diagram, the module appears to correspond to the "Co-Pro" block (highlighted in red) placed between the sensor and the main SoC (highlighted in blue). Both the module on the picture and the "Co-Pro" block on the diagram are linked to two 1Gb DDR2 SDRAM modules, confirming the match.
Starting with the X100S EXR Processor II, the "co-processor" functionality was likely (TBC) integrated into the single-chip module FF4427 first introduced in X100S camera.
Dual CPU
On the X-E2, the CPU0 returns a Main ID Register value of 0x411FC144, which clearly identifies it as a ARM Cortex-R4. (For the values of many other co-processor registers see EXR II CPU)
Note: the XPro-1 schematic diagram indicates the presence of a single ARM1136J-S CPU, which appears to be a copy-paste error. This discrepancy could point to broader issues with the reliability of the schematic as a whole.
The ARM Cortex-R4 is typically designed for single-core implementations. While it supports features like lock-step operation where two cores run in tandem for fault tolerance and appear as a single core from a programming perspective. This is different from a conventional multi-core setup where each core operates independently.
Despite this, the EXR Processor Pro and EXR II firmware contain code that strongly suggests (for details see Does-XF1-have-dual-CPU?) simultaneous execution on two ARM CPUs, each running its own instance of the RTOS kernel.
If this interpretation of the code as utilizing dual CPUs is correct, it would be quite unique and could potentially be used to identify the underlying IP.