EXR II CPU - tiredboffin/fffw GitHub Wiki
Main ID (MIDR) = 0x411FC144
Implementer [31-24] 41 (ARM)
Variant [23-20] b0001
Architecture [19-16] b1111
Primary Part [15-4] 0xc14 (Cortex-R4)
Revision [3-0] b0100
Cache Type (CTR) = 0x8003C003
DminLine [19-16] b0011 (8 words on L1 data cache line)
IminLine [3-0] b0011 (8 words on L1 icache line)
MPU Type (MPUIR) = 0x00000800 (8 regions)
Current Cache Size ID (CCSIDR) = 0xF00FE019 (size 16K)
WT [31-31] 1 (Write through)
WB [30-30] 1 (Write back)
RA [29-29] 1 (Read allocation)
WA [28-28] 1 (Write allocation)
NumSets [27-13] 127 (Number of sets 128)
Associativity [12-3] 0x3 (Number of ways 4)
LineSize [2-0] 0x1 (8 words in cache line)
Current Cache Level ID (CLIDR) = 0x09000003
LoU [29-27] 1 (unification level 2)
LoC [26-24] 1 (coherency level 2)
Ctype1 [2-0] b011 (data and instruction cache implemented)
Cache Size Selection (CSSELR) = 0x00000000 (data L1 cache)
Auxiliary Control (ACTLR) = 0x00000020 (parity checking disabled)
BTCM Region = 0x00000000
ATCM Region = 0x40000010 (8K disabled)
TCM selection = 0x00000000
Build Options 1 = 0x40000000 (default high address for the TCM)
Build Options 2 = 0x008A5A10
NO_FPU [22] 0 (FPU is supported)
NO_MPU [21] 0 (MPU is supprted)
MPU_REGIONS [20] 0 (8 MPU regions)
BREAK_POINTS [19-17] 5 (6 break points)
WATCH_POINTS [16-14] 1 (2 watch points)
NO_A_TCM_INF [13] 0 (ATCM port is present)
Debug ID Register (DBGDIDR) =
WRPs [31-28] b0001 (2 watchpoint pairs)
BRPs [27-24] b0101 (6 break points)
Version [19-16] b0100 (ARMv7 Debug)
Variant [7-4] 1
Revision [3-0] 4
Debug ROM Address Register (DBGDRAR) = 0xFFFD0003
ROMADDR [31-12] 0xfffd0
UNK [11-2] 0x0
Valid [1-0] b11
Debug Self Address Offset (DBGDSAR) = 0x00004003
SELFOFFSET [31-12] 0x4
UNK [11-2] 0x0
Valid [1-0] b11
@FFF98000 = 0x00030001
- DBGDSAR value 0x4003 identifies CPU0, see Does-XF1-have-dual-CPU?
- The lower 3 bits of the 32-bit value at address 0xFFF9_8000 are used to select the boot image source, see EXR II bootrom