Design Log - thepinkmile/Enigma-NG GitHub Wiki

Enigma-NG Design Decision Log

Status: Active Project: Enigma-NG Author: Izzyonstage & GitHub Copilot Version: v1.0.0 Associated Hardware Revision: Rev A Last Updated: 2026-04-05

This file records key architectural and component decisions made during the design of the Enigma-NG system. Each entry captures the decision taken, the rationale behind it, the alternatives that were considered, and any constraints or caveats that future designers should be aware of.

Entries are numbered sequentially as DEC-NNN. Where a decision supersedes a previous one, the earlier entry is updated with a cross-reference.

DEC-001 — 3V3_ENIG Used Throughout; 3V3_SYSTEM Removed from BtB Interconnect

Status: Obsolete — superseded by DEC-037
Date: 2025
Category: Electrical
Area: Power Module, Controller Board, Link-Alpha connector

Decision

The 3V3_SYSTEM rail (sourced from the CM5 on the Controller Board) is not routed to the Power Module over the Link-Alpha BtB connector. All 3.3V logic within the Power Module (RJ45 LED anodes, I2C pull-ups, BATT_PRES_N pull-up, reset pull-up) is powered by 3V3_ENIG, generated locally by the Power Module LDO (U7).

Rationale

3V3_SYSTEM is a CM5-derived rail intended only for external peripheral interfaces (Ethernet, HDMI, USB 3.0 ports). Using it to power internal power-module logic would create a cross-domain

dependency and complicate sequencing.
Generating 3V3_ENIG locally on the Power Module gives a clean, independently-controlled 3.3V supply that is always present when the Power Module is powered, regardless of CM5 boot state.
Removing 3V3_SYSTEM from the Link-Alpha connector freed pins 21–24, which were reallocated to extend the 5V_MAIN delivery cluster and GND return path.

Alternatives Considered

Route 3V3_SYSTEM from CM5 over Link-Alpha and use it for RJ45 logic. Rejected: cross-domain dependency, sequencing risk, wasted connector pins.
Use a second small LDO on the Controller Board to produce a local 3.3V for CM5-adjacent logic. Rejected: unnecessary complexity given 3V3_ENIG already exists.

Impact

Pins 21–22: Reassigned from 3V3_SYSTEM → 5V_MAIN (supplemental power pins)
Pins 23–24: Reassigned from 3V3_SYSTEM → GND (supplemental return path)
Combined 5V_MAIN capacity: 18 pins × 0.5A = 9A (was 16 pins = 8A)
Diagnostic Bank-Alpha Pin 14: Reassigned from 3V3_SYSTEM → SW_LED_CTRL (GPIO 20) (subsequently updated; see DEC-009)

DEC-002 — PoE Option A2 Selected: Coilcraft POE600F-12LD

Status: Decided
Date: 2025
Category: Electrical
Area: Power Module PoE subsystem, T2 transformer, TPS23730 feedback network

Decision

The PoE transformer T2 uses a Coilcraft POE600F-12LD off-the-shelf ACF transformer (12V output, 60W, 200kHz, ≥1500Vrms isolation, SMT package). The remainder of the PoE chain uses TPS2372-4 (802.3bt Type 4 PD interface) and TPS23730 (ACF controller), with TPS23730 feedback resistors adjusted for the 12V output.

Rationale

Replaces a custom-wound transformer design (Option A: 15V, 8–16 week lead time, ~£35–46 BOM) with a catalogue part available from Coilcraft Direct.
Off-the-shelf: £3.54 qty-1, ~£1.86 volume, in stock. Lead time: days not weeks.
Same ACF topology as the custom design — only feedback resistors change. No PCB layout changes to high-current paths.
12V output falls within the TPS25980 eFuse UVLO/OVLO window (11V – 16.9V) with no additional buck stage needed.

Alternatives Considered

Option A (Custom T2, 15V): Higher voltage headroom. Rejected: custom winding, long lead time, cost.
Option C (Silvertel Ag59812-LPB integrated module): Higher integration, 95% efficiency, ~£19–27. Rejected: higher cost, fixed form factor, less flexibility for thermal management, vendor

lock-in.
Kinetic Technologies KPM5912: 85W, 93% efficiency. Rejected: not stocked by any UK/EU distributor.

Key Parameters

Parameter	Value
Part	Coilcraft POE600F-12LD
Output	12V nominal
Power	60W (Type 4 PD, 72W class)
Isolation	≥1500Vrms
Topology	Active Clamp Flyback (ACF)
Package	SMT
Price (qty-1)	~£3.54

DEC-003 — PoE Output 12V; OR-ing Priority Logic Required

Status: Decided
Date: 2025
Category: Electrical
Area: Power Module PoE output, OR-ing diode (LM74700-Q1), eFuse input

Decision

PoE outputs 12V (not 15V) into the OR-ing stage. Because 12V < 15V USB-C input, passive OR-ing would always prefer USB-C and ignore PoE. Active enable logic is implemented: the TPS2372-4 /PG signal drives the LM74700-Q1 gate control low when PoE is live, disabling the USB-C path.

Rationale

PoE is the primary field power source when no USB-C adapter is connected. It must not be silently overridden by USB-C passthrough.
TPS2372-4 /PG (power good, active low) is a clean indicator of a live 802.3bt PoE session.
LM74700-Q1 already provides the USB-C ideal diode function; gating its enable is a minimal-change approach.

Constraints

PoE UVLO: 11V. eFuse UVLO: 11V. No margin at UVLO floor — PoE cable must be within 1V drop budget.
eFuse ILIM utilisation at 12V worst case: 4.67A / 7A = 66.7% ✓ (within 75% derating target).

DEC-004 — Supercap Charge Current 0.5A Under PoE

Status: Superseded by DEC-029 (cell specification updated; 0.5A charge current constraint retained)
Date: 2025
Category: Electrical
Area: LTC3350 supercap charger, PoE power budget

Decision

When running on PoE (802.3bt Type 4, 72W budget), the supercap charge current is reduced to 0.5A (vs. up to 2A on USB-C/Battery). This limits peak PoE utilisation to 73.9% (53.2W / 72W) — within the 75% design rule ✓ (see Certification_Evidence §3.5).

Rationale

Full 2A supercap charging on PoE would push utilisation to ~98%, leaving <2W margin for transient loads.
0.5A charge current charges the 8× 25F supercap bank (2S4P, 50F total — Abracon ADCR-T02R7SA256MB) in approximately 9 minutes from depleted.
Normal system usage is expected to exceed 30–45 minutes per session (startup + configuration + use), making a 2-minute charge time acceptable.
This limitation should be documented in the User Manual with guidance that maximum system load is not recommended during the initial PoE power-up window.

Constraints

Steady-state PoE load (after caps charged): 50.3W / 72W = 69.9% utilisation ✓

DEC-005 — TPS25980 eFuse Replaces TPS259474L

Status: Decided
Date: 2025
Category: Electrical
Area: Power Module eFuse (U1)

Decision

The input eFuse uses a TPS25980 (7A ILIM, silicon-fixed 16.9V OVLO) rather than the originally considered TPS259474L (5.5A ILIM).

Rationale

TPS259474L 5.5A limit is insufficient for worst-case USB-C 15V path at 75W: 75W / 15V = 5.0A + 10% derating = 5.5A — already at the device limit with no headroom.
TPS25980 (TPS259804ONRGER) provides 7A ILIM (programmed via R3 = 210 Ω) and silicon-fixed 16.9V OVLO, which neatly caps the battery charge voltage window.

OVLO Constraint

eFuse OVLO is 16.9V silicon-fixed (TPS259804ONRGER — no external programming resistor).
BMS must be configured for 4.1V/cell maximum charge (16.4V for 4S) to maintain a ≥0.5V margin.
BMS configurations using 4.2V/cell (16.8V) are not compatible with this eFuse and must not be used.

⚠️ Variant Lock — Do NOT change this MPN

The TPS25980 family uses a digit after TPS25980 to select the OVLO behaviour:

Variant	OVLO	Status
TPS259804ONRGER	16.9V silicon-fixed	✅ CORRECT — use this
TPS259807	No OVLO feature	❌ WRONG — do not use
TPS259803	No OVLO feature	❌ WRONG — do not use

This variant has been erroneously swapped to TPS259807 in previous review rounds. The 04 digit must not be changed without explicit documented justification.

DEC-006 — STUSB4500 Negotiates 15V/5A (75W)

Status: Decided
Date: 2025
Category: Electrical
Area: Power Module USB-C PD handshake (STUSB4500), USB-C adapter requirement

Decision

The STUSB4500 standalone PD sink is programmed to negotiate 15V/5A (75W) from the wall adapter or USB-C PD source. Earlier documentation incorrectly stated 15V/3A.

Rationale

3A (45W) is insufficient for worst-case system load (CM5 at 25W + rotors + supercap charging).
5A (75W) provides headroom and aligns with the 75% derating target at the eFuse.
Users must use a USB-C PD adapter rated for at least 75W (15V/5A or 20V/5A with appropriate negotiation cap).

DEC-007 — Dual Interleaved LMQ61460-Q1 5V Buck (12A)

Status: Decided
Date: 2025
Category: Electrical
Area: Power Module 5V Buck (U2A/U2B)

Decision

Two LMQ61460-Q1 buck regulators are used in a dual interleaved configuration, providing a combined 12A output at 5V. Earlier documentation referenced a single LM61460-Q1 (6A).

Rationale

Single 6A device is insufficient for CM5 at 25W (5A) + other 5V loads.
Interleaved dual phase reduces input/output ripple and distributes thermal load.
12A capacity aligns with the 9A+ delivery capability of the updated Link-Alpha pin cluster.

DEC-008 — TPS25750 Emulates 5V/5A PD Profile to CM5

⚠️ Superseded by DEC-012 — TPS25750 replaced with TPS25751DREFR. See DEC-012.

Status: Superseded by DEC-012
Date: 2025
Category: Electrical
Area: CM5 USB-C PD emulator (TPS25750)

Decision

The TPS25750 PD emulator advertises a 5V/5A profile to the CM5 internal USB-C port.

Rationale

The CM5 Linux OS will generate a "low power" warning if PD negotiation does not complete at or above 5V/5A (25W).
5V/5A is the minimum advertisement to suppress this warning and allow unrestricted CPU/GPU boost operation.

DEC-009 — Diagnostic Bank-Alpha Pin 14 Reassigned to SW_LED_CTRL

Status: Decided
Date: 2025 (GND); superseded by final design (SW_LED_CTRL)
Category: Electrical
Area: Controller Board Diagnostic Bank-Alpha connector

Decision

Diagnostic Bank-Alpha pin 14 was initially reassigned from 3V3_SYSTEM to GND, following the removal of the 3V3_SYSTEM rail from all BtB interconnects (see DEC-001). In the subsequent design pass that added SW_LED_CTRL (GPIO 20) to the Link-Alpha signal set, pin 14 was reallocated to SW_LED_CTRL to expose the LED-arbitration handshake at the diagnostic header.

Final assignment: Bank-Alpha Pin 14 = SW_LED_CTRL (GPIO 20, CTRL → PM, HIGH = CM5 in control of SW1 RGB LED).

Rationale

3V3_SYSTEM is no longer available at the Power Module side of this debug header.
SW_LED_CTRL is a useful diagnostic probe point — it shows whether the CM5 has taken control of the RGB LED from the hardware oscillator fallback path.
GND is freely available on pins 19–20; a redundant GND at pin 14 added no diagnostic value.

DEC-010 — INC-14 DEFERRED: Diagnostic Bank ESD Protection (Post-Prototype)

Status: Deferred — Accepted risk for prototype stage
Date: 2025
Category: Electrical
Area: Controller Board Diagnostic Bank-Alpha / Bank-Beta connectors

Decision

ESD protection on the diagnostic bank connectors is deferred to post-prototype evaluation. No TVS diodes or series resistors are added to diagnostic header signals at this stage.

Rationale

Diagnostic headers are internal, accessed only by engineers with ESD precautions during development.
Adding ESD protection to every diagnostic pin adds cost, board space, and complexity before there is validated evidence that it is needed.
Risk accepted for prototype: controlled lab environment, trained operators, no field exposure.

Post-Prototype Action Required

During first prototype test phase, evaluate signal integrity and ESD sensitivity on diagnostic lines.
If any diagnostic lines are exposed to field conditions (e.g., external test connectors), add series 33Ω + TVS per line.
Document findings and update this log with the final resolution.

DEC-011 — All Power Rails on Power Module; 3V3_ENIG Serves Rotor Stack

Status: ✅ RESOLVED
Date: 2025
Category: Electrical
Area: Power Module islands, Controller Board routing, rotor stack power source

Decision

All power rails are generated on the Power Module. The Controller Board's role is purely to route power rails onward to downstream boards — it does not generate any rails itself. The rotor stack is powered by the existing 3V3_ENIG rail (TPS75733KTTRG3 LDO, 3A). There is no separate Rotor Buck; the erroneous "3.3V/5A Rotor Buck" specification was a confusion with the 5V/5A CM5 rail and has been removed.

Rationale

Centralising all power generation on the Power Module simplifies thermal management (all heat dissipation in one shielded enclosure with dedicated thermal zone).
Reduces the risk of ground loops and cross-domain sequencing issues.
The Controller Board as a routing layer keeps its design cleaner and easier to revise independently.
3V3_ENIG (3A) covers all 3.3V consumers: CPLDs, USB-JTAG, I2C logic, control signals, and the rotor stack.
Settings Board RGB indicators are powered from 5V_MAIN via the Stator/Settings 6-pin harness; only their control logic remains on 3V3_ENIG.
ROTOR_EN (CM5 GPIO 16) enables/disables the 3V3_ENIG LDO for sequenced rotor power-up — a control signal only.

Architectural Rule (permanent)

All power rails are generated on the Power Module. The Controller Board routes rails to downstream boards only. No buck converters, LDOs, or other power-generating components belong on the Controller Board.

Impact

README.md: Removed erroneous "Dedicated 3.3V/5A Buck" from Controller Board section; 3V3_ENIG correctly listed as Power Module output serving CPLDs, logic, and rotor stack.
Power_Module/Design_Spec.md: 3V3_ENIG scope updated to include rotor stack; 3-island Power Plane retained.
Controller/Design_Spec.md: ROTOR_EN clarified as LDO enable signal to Power Module.
Rotor/Design_Spec.md: Power source updated from "Controller Board Island C" to "Power Module 3V3_ENIG rail".

Previously Conflicting References (now corrected)

README.md placed the Rotor Buck under the Controller Board section.
Rotor/Design_Spec.md said "sourced from the Controller Board's Island C".

DEC-012 — U4 TPS25750 Replaced with TPS25751DREFR (NRND Resolution)

Status: ✅ RESOLVED
Date: 2026-04-03
Category: Electrical
Area: Power Module U4, schematic, PCB footprint

Decision

Replace TPS25750 (NRND — Not Recommended for New Designs) with TPS25751DREFR (PD3.1 certified DRP controller, WQFN-38 6×4mm).

Rationale

PD emulation for U4 is required: the Raspberry Pi CM5 must negotiate a 5V/5A (25W) contract from the USB-C PD source to prevent the OS from issuing under-voltage warnings and throttling the system.
The TPS25751D variant includes the integrated 20V/5A bi-directional power path and a 5V/3A source switch in one package — appropriate for DRP operation that can advertise and deliver the 5V/5A

profile to the CM5.
TPS25751 is USB-IF PD3.1 certified (TID#10306); TPS25750 was PD2.0 only and is NRND.
STUSB4500 (U5) handles the USB-C sink path; TPS25751 (U4) handles the source/emulation path. These are separate and complementary roles.

Impact

Package: TPS25750 was QFN-28; TPS25751DREFR is WQFN-38 6×4mm. KiCad symbol and footprint to be created when schematic capture begins.
Mouser: 595-TPS25751DREFR; DigiKey: 296-TPS25751DREFRCT-ND; JLCPCB: C30169739.

DEC-013 — L3 EMI Inductor Changed to Bourns SRP1265A-100M

Status: ✅ RESOLVED
Date: 2026-04-03
Category: Electrical
Area: Power Module L3, PCB footprint

Decision

Replace Würth 7447789100 with Bourns SRP1265A-100M as L3 (EMI DM Pi-filter inductor).

Rationale

Würth 7447789100 is not available in any public distributor catalog (not found at DigiKey, Mouser, Farnell, or on the Würth public website). Sourcing without a Würth rep contact is not feasible.
Bourns SRP1265A-100M is a direct functional equivalent: 10µH, 15.5A Isat (exceeds 14.5A target with 21% headroom), DCR=16.5mΩ max (better than the original 20mΩ spec), shielded molded SMD.
Widely stocked: Farnell ~2,741 pcs; Mouser (652-SRP1265A-100M); DigiKey (SRP1265A-100MCT-ND).

Impact

⚠️ Package footprint change: SRP1265A-100M is 13.5×12.5×6.2mm vs 7447789100's 12.5×12.5×6.0mm. PCB land pattern for L3 must use the Bourns 13.5×12.5mm footprint. Clearance to adjacent

components should be checked during layout.

DEC-014 — Controller Board Uses ERF8 (Female) on Both BtB Connectors for Blind-Mate Assembly

Status: ✅ RESOLVED
Date: 2026-04-04
Category: Electrical
Area: Controller J1 (Link-Alpha), Controller J2 (Link-Beta), Consolidated BOM connector inventory

Decision

Both BtB connectors on the Controller Board use the ERF8 female socket: J1 (Link-Alpha) uses ERF8-040-05.0-S-DV-K-TR and J2 (Link-Beta) uses ERF8-020-05.0-S-DV-K-TR. The mating male plugs are fitted to the Power Module (J1, ERM8-040) and the Stator Board (J8, ERM8-020-05.0-S-DV-K-TR) respectively.

Rationale

During mechanical assembly, the Controller Board slides into the enclosure and must simultaneously engage with two boards along its back edge — the Power Module (J1) to one side and the Stator (J2) to the other. Using female sockets on the Controller allows guided blind-mate engagement in a single insertion motion, with the mating male pins on the peripheral boards providing positive alignment. Placing male headers on the Controller would require both peripheral boards to be precisely pre-positioned before the Controller could be inserted, significantly complicating assembly.

Connector Assignment Summary

Board	Connector	Gender	Part
Controller	J1 (Link-Alpha, from Power Module)	Female	ERF8-040-05.0-S-DV-K-TR
Controller	J2 (Link-Beta, to Stator Board)	Female	ERF8-020-05.0-S-DV-K-TR
Power Module	J1 (Link-Alpha plug)	Male	ERM8-040-05.0-S-DV-K-TR
Stator Board	J8 (Link-Beta plug)	Male	ERM8-020-05.0-S-DV-K-TR

Impact

Controller BOM J2 updated from ERM8 (male) to ERF8 (female); JLCPCB C-number to be verified.
Controller §2 narrative updated to reflect ERF8 on Link-Beta.
No electrical impact — connector is signal-transparent; pin assignments unchanged.

DEC-015 — LINK-BETA Connector Reduced from 80-pin to 40-pin (ERF8-020 / ERM8-020)

Status: ✅ RESOLVED
Date: 2026-04-04
Category: Electrical
Area: Controller Board (J2), Stator Board (J8), Consolidated BOM
Amended by: DEC-036 (2026-04-18), DEC-037 (2026-04-18)

Decision

The LINK-BETA Board-to-Board connector is reduced from 80-pin (ERF8-040 / ERM8-040) to 40-pin (ERF8-020-05.0-S-DV-K-TR / ERM8-020-05.0-S-DV-K-TR). The table below records the original post-reduction allocation; the current active allocation is defined by DEC-037.

Pin	Signal	Direction	Notes
1	GND	—	JTAG leading shield
2	TCK	CTRL→Stator	JTAG clock
3	GND	—	TCK/TMS inter-pin shield
4	TMS	CTRL→Stator	JTAG mode select
5	GND	—	TMS/TDI inter-pin shield
6	TDI	CTRL→Stator	JTAG data in
7	GND	—	TDI/SPARE inter-pin shield
8	SPARE	—	Freed by DEC-031 (was SYS_RESET_N — migrated to I²C U_EXP2 GPA[7] @ 0x21)
9	GND	—	JTAG trailing shield
10	GND	—	Isolation moat pin 1
11	GND	—	Isolation moat pin 2
12	SPARE	—	Freed by DEC-031 (was ENC_IN[0] — migrated to I²C U_EXP1 @ 0x20)
13	SPARE	—	Freed by DEC-031 (was ENC_IN[1])
14	SPARE	—	Freed by DEC-031 (was ENC_IN[2])
15	SPARE	—	Freed by DEC-031 (was ENC_IN[3])
16	SPARE	—	Freed by DEC-031 (was ENC_IN[4])
17	SPARE	—	Freed by DEC-031 (was ENC_IN[5])
18	GND	—	Inter-group shield
19	SPARE	—	Freed by DEC-031 (was ENC_OUT[0] — migrated to I²C U_EXP1 @ 0x20)
20	SPARE	—	Freed by DEC-031 (was ENC_OUT[1])
21	SPARE	—	Freed by DEC-031 (was ENC_OUT[2])
22	SPARE	—	Freed by DEC-031 (was ENC_OUT[3])
23	SPARE	—	Freed by DEC-031 (was ENC_OUT[4])
24	SPARE	—	Freed by DEC-031 (was ENC_OUT[5])
25	GND	—	ENC_OUT / TTD_RETURN shield
26	TTD_RETURN	Stator→CTRL	JTAG TDO short-path return (bypasses rotor stack)
27	GND	—	TTD_RETURN shield
28–35	3V3_ENIG	PM→Stator	Power pass-through from Link-Alpha; 8 pins × 0.5A = 4.0A
36–40	GND	—	Power return (5 pins)

Rationale

Logic boards downstream of the Stator (Encoder, Reflector, Extension) are 3V3-only — they require no 5V_MAIN rail. Removing 5V_MAIN from LINK-BETA and rationalising the signal set results in exactly 40 signals. The JTAG block has 5 internal GND shield pins (self-shielded at low-moderate MHz), so only a 2-pin GND moat is needed between JTAG and the data zone. 8 × 3V3_ENIG pins deliver 4.0A — adequate for the worst-case 30-rotor stack (2.11 A per Power_Budgets.md). 5 GND return pins plus the 10 other GND pins throughout the connector provide adequate return paths.

Poka-Yoke Safety Note

The 80-pin LINK-ALPHA (ERF8-040) and 40-pin LINK-BETA (ERF8-020) on the Controller Board are physically incompatible — the mating connectors cannot be inserted into the wrong socket. This provides a mechanical safeguard against mismating during prototype bring-up.

Alternatives Considered

Keeping 80-pin connector with unused pins. Rejected: unnecessary connector cost and PCB area; larger connector on the Stator increases stack height with no benefit.

Impact

Controller J2: ERF8-040 → ERF8-020-05.0-S-DV-K-TR (female, 40-pin)
Stator J8: ERM8-040 → ERM8-020-05.0-S-DV-K-TR (male, 40-pin)
DEC-014 connector table updated (see cross-ref below).

Cross-ref

DEC-014 (gender assignment rationale remains valid; part numbers updated). DEC-031 (pins 8, 12–17, and 19–24 freed — SYS_RESET_N and ENC_IN/OUT migrated to I²C). DEC-036 (freed monitor block reallocated into grouped 5V_MAIN / 3V3_ENIG / GND rails).

DEC-016 — JTAG Controlled Impedance and Series Termination

Status: ✅ ADOPTED
Date: 2026-04-05
Category: Electrical
Area: Controller Board, Stator Board, Encoder Board, Reflector Board (noted), Extension Board (noted)

Decision

All JTAG signal traces on 4-layer and 6-layer PCBs are specified at 50 Ω controlled impedance (0.127 mm / 5 mil trace width on outer layers over a contiguous GND plane). Series termination resistors are added at every cable-driving JTAG output using 75 Ω (to match the ~100 Ω impedance of alternating-GND IDC ribbon cable), and at every intra-board or BtB-driving JTAG output using 33 Ω (to match the 50 Ω PCB trace impedance).

Full signal-swing analysis confirms the destination CPLD receives full logic swing (3.3 V) in all cases. The open-circuit reflection at the high-impedance CPLD input doubles the incoming wave back to full voltage; the series resistor controls the return reflection, not the final voltage.

Full analysis, all options considered, and trace width calculations

See design/Electronics/Investigations/JTAG_Integrity.md.

Summary of additions per board

Board	Refs	Value	Purpose
Controller	R4, R5, R6	33 Ω 0603	~~TCK / TMS / TDI series R after 74LVC2G125 buffer, before LINK-BETA~~ Moved to JDB — see DEC-024
Stator	R7–R9	75 Ω 0603	TCK → J4 / J5 / J6 encoder port outputs
Stator	R10–R12	75 Ω 0603	TMS → J4 / J5 / J6 encoder port outputs
Stator	R13–R15	75 Ω 0603	TDI chain drive: Stator CPLD TDO→J4, J4 return→J5, J5 return→J6
Encoder	R7	33 Ω 0402	CPLD1 TDO → CPLD2 TDI (intra-board, match 50 Ω PCB trace)
Encoder	R8	75 Ω 0402	CPLD2 TDO → J2 connector (ribbon cable drive back to Stator)
JDB	R6, R7, R8	33 Ω 0402	TCK / TMS (after U5 buffer) / TDI series damping — before J2 JTAG header

Update (detailed design): U5 (SN74LVC2G125DCUR buffer) and series damping resistors relocated from Controller to JDB during detailed design. LINK-BETA is confirmed as a direct Board-to-Board connector (no cable), so 33 Ω series damping applies throughout (not 75 Ω cable-driving rule). Controller JTAG lines (TCK, TMS, TDI, TTD_RETURN, VREF) are pass-through — routed directly from JDB hat-header to LINK-BETA without active components. See DEC-024.

Trace width rule added to all 4-layer and 6-layer boards: 0.127 mm (5 mil) for all JTAG signal traces on outer layers over a GND plane.

2-layer boards (Reflector, Extension): Controlled impedance not practical — 50 Ω would require a 2.82 mm trace (see design/Electronics/Investigations/JTAG_Integrity.md §4). Series termination at cable-driving ends of adjacent boards provides sufficient protection. Existing Reflector R1 (22 Ω) retained as end-of-chain damping.

Superseded (partial): The Reflector and Extension 2-layer limitations above are superseded by DEC-017, which upgrades both boards to 4-Layer JLC04161H-7628. Both boards now have a solid L2 GND plane and route JTAG on L1 at 0.127 mm (50 Ω), consistent with all other 4-layer boards.

Rationale

Achieving 100 Ω PCB traces (to perfectly match the IDC ribbon cable impedance) is physically impossible on JLCPCB standard 4-layer/6-layer stackups — the required trace width is negative (see calculation in design/Electronics/Investigations/JTAG_Integrity.md §4). The 50 Ω + 75 Ω hybrid approach provides the best achievable impedance match to the cable while remaining within manufacturing design rules.

Alternatives Considered

No termination (Option A): Rejected — multiple re-reflections at 10 MHz risk false TCK edges.
50 Ω PCB + 33 Ω series R (Option B): Acceptable but leaves 33% reflection at PCB-to-cable transition unabsorbed.
100 Ω PCB + 82 Ω series R (Option C, ideal): Rejected — not achievable on standard stackup.

Cost Impact

Additional BOM cost per full system < £0.05. No JLCPCB impedance certification required for prototype; trace widths self-calculated and within ±10% of target. See design/Electronics/Investigations/JTAG_Integrity.md §9.

DEC-017 — Minimum 4-Layer Stackup for All Non-Controller Boards

Status: ✅ ADOPTED
Date: 2026-04-05
Category: Electrical
Area: Reflector Board, Extension Board (all other boards already compliant)

Decision

All PCBs in the Enigma-NG system shall use a minimum of 4-layer stackup (JLCPCB JLC04161H-7628). The Controller Board and the Power Module Board are the only exceptions and retain their 6-layer JLC06161H-2116 stackup: the Controller for high-speed 5 Gbps differential pair requirements, and the Power Module for high-current power delivery.

Standard 4-layer layer mapping for all non-Controller boards

Layer	Function
L1	Signal (JTAG, data routing) — top
L2	GND plane — solid contiguous copper
L3	3V3_ENIG power plane
L4	Signal (data routing, branding data plate) — bottom

Exception — JTAG Daughterboard: The JDB uses an inverted stackup: L1=GND plane + SMT component pads (component side, faces Controller), L2=signal traces, L3=power pours, L4=GND shield (exterior face). This inversion places components on the face that mates with the Controller Board hat-headers, consistent with single-side JLCPCB assembly. See JTAG_Daughterboard/Design_Spec.md §4.

Boards affected (updated)

Board	Previous	New
Reflector	2-Layer 1.6mm FR4 / 1oz	4-Layer JLC04161H-7628 / 2oz
Extension	Layer count unspecified	4-Layer JLC04161H-7628 / 2oz

Boards already compliant (no change)

Board	Stackup	Notes
Stator	4-Layer JLC04161H-7628	✅ Unchanged
Encoder	4-Layer JLC04161H-7628	✅ Unchanged
Rotor	4-Layer JLC04161H-7628	✅ Unchanged
Controller	6-Layer JLC06161H-2116	✅ Exception — high-speed stackup retained
Power Module	6-Layer JLC06161H-2116	✅ Exception — high-current power delivery stackup retained

Impact

The "2-layer uncontrolled impedance" notes for Reflector and Extension in DEC-016 are superseded. Both boards now have a solid L2 GND plane and can route JTAG on L1 at 0.127 mm (50 Ω controlled impedance), consistent with all other 4-layer boards. design/Electronics/Investigations/JTAG_Integrity.md §3.1, §3.3 (now historical), and §8 trace table have been updated accordingly.

Rationale

Uniform stackup: Consistent JLC04161H-7628 across all non-Controller boards eliminates stackup-dependent trace impedance variation, reducing signal behaviour differences between boards.
Solid GND on every board: All boards now have a contiguous L2 GND plane, enabling 50 Ω controlled impedance JTAG routing across the entire system.
EMC/EMI improvement: Solid GND and power planes on all boards reduce radiated emissions and improve common-mode noise rejection across the rotor stack and encoder cabling.
Manufacturing speed: JLC04161H-7628 is JLCPCB's most common 4-layer stackup, with higher stock availability and faster turnaround than 2-layer special orders or less common stackups.
Cost: Marginal price difference between 2-layer and 4-layer at JLCPCB prototype quantities; outweighed by signal integrity and EMC benefits.

Alternatives Considered

Retain 2-layer Reflector/Extension: Rejected — inconsistent stackup creates impedance discontinuities in the JTAG chain and leaves an uncontrolled segment at the reflector end.
Use different 4-layer stackup per board: Rejected — non-uniform dielectric parameters would require separate trace width calculations per board and add unnecessary design complexity.

DEC-018 — Connector Pinout Ownership Model

Status: Adopted
Date: 2026-04-05
Category: Electrical
Area: All Boards — Documentation Architecture

Decision

Each multi-board connector interface shall have a single Definition Owner — the board whose Board_Layout.md (or Design_Spec.md where no Board_Layout exists) contains the authoritative pin-by-pin table for that interface. All other boards that mate with that connector must not duplicate the pin table; instead they include a short cross-reference note of the form:

Connector Definition Owner: [OwnerBoard]/Board_Layout.md — [Section]. This board uses the mating connector. See BOM for part number.

This rule prevents the class of drift errors where two boards define the same connector differently (e.g. Pin 2 = GND on one board, SYS_RESET_N on another). When a conflict is found, the owner's definition is authoritative.

Ownership Register

Interface	Connector(s)	Definition Owner	Authoritative Section
LINK-ALPHA	PM J1 ↔ Controller J1 (80-pin ERM8/ERF8)	Power Module	`Power_Module/Board_Layout.md — LINK-ALPHA`
LINK-BETA	Controller J2 ↔ Stator J8 (40-pin ERM8/ERF8)	Controller	`Controller/Board_Layout.md — LINK-BETA`
Reflector/Extension Link	Stator J7 ↔ Extension J7/J8 ↔ Reflector J4 (16-pin 2×8)	Stator	`Stator/Board_Layout.md — J7`
Encoder Ports	Stator J4/J5/J6 ↔ Encoder J2 (26-pin 2×13)	Stator	`Stator/Board_Layout.md — J4–J6`
Rotor Interface	Stator J1–J3 ↔ Rotor 1 → … → Rotor 30 → Reflector J1–J3 (serial chain; Extension J1–J6 at group boundaries)	Rotor	`Rotor/Design_Spec.md §3.4`
JTAG Daughterboard headers	JDB J1 (USB 5-pin) + J2 (JTAG 10-pin)	JTAG Daughterboard	`JTAG_Daughterboard/Board_Layout.md`

Rationale

LINK-ALPHA → Power Module: The Power Module is the upstream power provider; it defines what rails and signals it places on the cable. The Controller is the downstream consumer.
LINK-BETA → Controller: The Controller is the JTAG chain master. It originates TCK, TMS, TDI, SYS_RESET_N, and the ENC data bus. The Stator is the passive backplane receiver.
Reflector/Extension Link → Stator: The Stator is the signal origin for all ENC data, power, and TTD_RETURN carried on this cable. Extension and Reflector are passive pass-throughs or endpoints.
Encoder Ports → Stator: The Stator drives all three encoder cables and has the complete chain routing logic for TDI/TDO sequencing across J4/J5/J6. The Encoder boards are the downstream receivers.
Rotor Interface → Rotor: The Rotor defines its own physical interface — both the connector type (mechanical) and the signal mapping. Stator, Extension, and Reflector must comply with the Rotor's mechanical interface, not the other way round.
JTAG Daughterboard → itself: Self-contained module with no cross-board mating conflicts.

Alternatives Considered

Central Interfaces.md document: Rejected — separates pin definitions from the board they belong to, making it harder to keep in sync during incremental design changes. Per-board ownership with cross-references is more maintainable.
Both sides document the full table: Rejected — this is the exact pattern that caused the REF-03 Pin 2 conflict and the REF-01 16/20-pin mismatch found in the April 2026 deep-dive review.

DEC-019 — PoE Transformer Topology: ACF (Option A) Selected

Status: ✅ Adopted
Date: 2026-04-05
Category: Electrical
Area: Power Module — T2 transformer, TPS23730 operating mode, input EMI filter

Decision

The Power Module retains the Active Clamp Flyback (ACF) topology with the Coilcraft POE600F-12LD transformer. The TPS23730 operates in ACF mode, driving an external active clamp MOSFET complementary to the primary switch. The Coilcraft transformer is procured order-direct from coilcraft.com and supplied to JLCPCB as a consignment part.

No change is made to the T2 transformer, the TPS23730 mode configuration, or the active clamp circuit.

Full investigation detail: design/Electronics/Investigations/PoE_Investigation.md

Rationale

A thorough search confirmed that no ACF PoE isolation transformer for 60W / 36–57V input is stocked by any mainstream authorised distributor (DigiKey, Mouser, Farnell, Arrow). The Coilcraft POE600F family was co-developed with TI specifically for the TPS23730 reference design; no competing catalogue part exists.

The only standard-distributor alternative identified was the Bourns PDC060-FD20A12S — a standard flyback transformer available from DigiKey. Switching to this part (Option B) would have required:

Disabling TPS23730 ACF_GD (ACF gate drive pin)
Removing the active clamp MOSFET and capacitor
Adding an RCD clamp (3 SMD components)
Verifying PSR auxiliary winding compatibility (unconfirmed)

After detailed EMI/EMC analysis, Option B was rejected on technical grounds. Key findings:

Criterion	Option A (ACF)	Option B (Flyback)
Primary switching	ZVS — no hard dV/dt event	Hard switching — fast dV/dt
Drain spike at turn-off	None — energy recycled by clamp	Present — RCD clamp clips but does not eliminate
CM/DM conducted EMI	Low	15–25 dB higher before input filter
Input EMI filter size	Smaller / fewer components	Larger / more complex
CISPR 32 Class B margin	Comfortable	Tight — may require design iteration
Efficiency	88–92%	85–90%
Extra dissipation	—	~1–2W at full load
PSR aux winding verified	✅ TI reference design	⚠️ Unverified for Bourns PDC060

The Coilcraft direct-order model is accepted as a specialist procurement path, consistent with industry practice for catalogue magnetics.

Alternatives Considered

Bourns PDC060-FD20A12S (Option B — flyback PSR): Rejected — hard-switching topology causes significantly higher conducted and radiated EMI, requires a larger input EMI filter, does not eliminate procurement complexity (shifts effort from transformer sourcing to filter design), and adds ~1–2W thermal load to an already thermally constrained module.
Würth WE-FB range: Rejected — entire range has a maximum input voltage of 36V (insufficient for PoE 36–57V input) and is keyed to Linear Technology LT-series controllers.
Change PoE controller ecosystem: Not evaluated — would constitute a major redesign and is out of scope.

DEC-020 — GND_CHASSIS Rib Clearway ENIG Bond

Status: Accepted — 2026-04-08
Date: 2026-04-08
Category: Electrical
Area: Power Module — Supercap Block Assembly & Board Layout
References: QUE-001, Certification_Evidence.md §2.2

Decision

The 3.0mm rib clearway gaps between supercap cells shall have:

Exposed ENIG strip (L1): Solder mask opened in the rib clearway gap on the top copper layer (L1), connected to the GND_CHASSIS net. Minimum strip width 1.5mm, running the full depth of the rib contact zone. The aluminium enclosure rib makes direct electrical contact with the PCB GND_CHASSIS copper, providing a distributed HF chassis ground bond at the supercap block location.
Polyimide (Kapton) tape on supercap bodies: Each supercap cell shall be wrapped with a minimum of one layer of 2-mil (50µm) polyimide tape prior to installation, to electrically insulate the cell body from the aluminium compression ribs and prevent short circuits.
Conductive elastomer gasket strip: A self-adhesive conductive elastomer or conductive foam gasket strip (≤3mm wide, full rib contact depth) shall be applied to the rib face or PCB contact zone to accommodate manufacturing tolerances and ensure positive, reliable electrical contact under compression. Part to be selected at mechanical design phase when rib geometry is confirmed.

Rationale

The combined structure — aluminium Can lid, compression ribs, conductive gasket, PCB ENIG strip, and GND_CHASSIS copper pour — forms a near-complete Faraday cage around the supercap block, improving shielding of the high-capacitance energy storage element from the rest of the board.

Compatibility with single-point GND_CHASSIS bond rule

The single-point rule governs signal GND → GND_CHASSIS crossings. Rib contact bonds are enclosure-to-GND_CHASSIS connections — both within the chassis domain — and do not create additional signal-to-chassis bonds. The rule is maintained.

Other boards

Deferred pending mechanical design documentation. Controller Board Mechanical_Design.md §3 notes the prototype uses a 3D-printed chassis (no conductive rib contact); this decision will be revisited when metal chassis dimensions are finalised. Stator/Encoder/Rotor mechanical designs are not yet written.

DEC-021 — Supercapacitor Bank Upgrade: 2×2 2S2P → 2×3 2S3P

Status: Superseded by DEC-029 (arrangement 2S3P retained; cell capacitance updated 22F → 25F Abracon)
Date: 2026-04-08
Category: Electrical
Area: Power Module — Supercap Bank, Board Layout, Hold-up Specification
References: DR-PM-07, DR-PM-09, DEC-020

Decision

The supercapacitor bank is upgraded from a 2×2 (4-cell, 2S2P) to a 2×3 (6-cell, 2S3P) arrangement, with the inter-cell air gap increased from 2.0mm to 3.0mm.

Parameter	Previous	New
Cell count	4 (C_SC1–4)	6 (C_SC1–6)
Arrangement	2×2	2×3
Configuration	2S2P	2S3P
Inter-cell gap	2.0mm	3.0mm
Cell pitch	14mm	15mm
Block footprint	28mm × 28mm	30mm × 45mm
Shadow zone	32mm × 32mm	34mm × 49mm
Effective capacitance	22F at 5.4V	33F at 5.4V
Hold-up energy	72.4J	108.6J
Hold-up duration @ 5W	≥14.5s	≥21.7s
Charge time (depleted)	~2 min	~3 min

Rationale

50% more hold-up: 33F vs 22F provides ≥21.7 seconds at 5W — a more comfortable shutdown window and headroom for higher CM5 load profiles at prototype bring-up.
LTC3350 compatibility: No IC change required. LTC3350 is configured for 2 cells in series; each series position now has 3×22F in parallel (66F per position). CELLS register unchanged. RICHARGE (0.5A charge current limit) unchanged; charge time increases ~3 minutes from depleted.
Wider gap (3mm): The increased inter-cell gap from 2.0mm to 3.0mm provides adequate clearance for the 2-mil Kapton tape wrap (DEC-020), the conductive elastomer gasket strip, and the aluminium enclosure compression ribs, while maintaining margin for manufacturing tolerances.
Board space: The Power Module board dimensions are not yet fixed; the design is being built around this component block. The increased footprint (30mm × 45mm vs 28mm × 28mm) is accepted.

Post-decision update (2026-04-08, checkpoint 025): The 22F generic cells specified above were subsequently replaced with Abracon ADCR-T02R7SA256MB (25F/2.7V) when a verified in-stock THT radial supercap was sourced. The 2S3P arrangement and all mechanical dimensions are unchanged. Effective capacitance increases from 33F to 37.5F; hold-up increases from 21.7 s to ≥24.8 s. The values 22F / 33F / 21.7 s are historical and must not be restored.

DEC-022 — JDB FT232H Clock Source: Dedicated 12MHz SMD Crystal Selected

Status: Obsolete — superseded by DEC-037
Date: 2026-04-06
Category: Electrical
Area: JTAG Daughterboard — Clock Source (FT232H)

Decision

Dedicated 12MHz SMD passive crystal (Y1) on the JDB PCB. CM5 GPCLK0 option rejected.

Context

During JDB detailed design review, two issues were identified:

The original design incorrectly specified a 24MHz HC-49 through-hole crystal. The FT232H datasheet requires a 12MHz reference — its internal PLL multiplies 12MHz × 40 to generate 480MHz for USB Hi-Speed operation. 24MHz is outside specification.
An alternative was considered: routing a clock from the CM5 GPCLK0 output (GPIO4) to the FT232H OSCI pin instead of a dedicated on-board crystal.

Options Considered

Option	Description	Verdict
A	CM5 GPCLK0 (GPIO4) routed through Controller hat-header to FT232H OSCI	Rejected
B	Dedicated 12MHz passive SMD crystal (Y1) on JDB PCB	Selected

Option A — Rejected reasons:

Signal path: CM5 GPIO4 → Controller board → hat-header pin → JDB OSCI is long and noise-prone
GPIO clock jitter from BCM is unsuitable as a USB PLL reference clock
Creates a CM5 boot-order dependency — FT232H cannot enumerate on USB until CM5 configures GPCLK0
Adds routing and firmware complexity with no benefit over a $0.07 crystal

Option B — Selected:

Standard FTDI reference design approach; clean stable clock source
No boot dependency; FT232H enumerates immediately on USB connect
Component: YXC X322512MSB4SI (JLCPCB C9002), SMD3225-4P, 12MHz, 20pF, ±20ppm, Basic part
Crystal load capacitors: C10–C11 = 33pF C0G 0402 (sets 20pF load capacitance)

Impact

design/Electronics/JTAG_Daughterboard/Design_Spec.md: Y1 corrected to 12MHz SMD3225-4P (C9002); C10–C11 added; text references updated.

DEC-023 — JDB GND_CHASSIS Omitted; Mounting Holes Tied to GND

Status: Decided
Date: 2026-04-06
Category: Electrical
Area: JTAG Daughterboard — Grounding & EMC

Decision

The JTAG Daughterboard (JDB) does not implement a GND_CHASSIS net. Mounting holes are included for mechanical stability via conductive standoffs to the Controller board; the copper pours around those mounting holes are tied to GND (circuit return). No dedicated chassis bond pad, stitching via, or GND_CHASSIS net is present on the JDB.

Cross-reference: DEC-039 keeps the single Power Module bond rule but now makes this JDB treatment the generic exception for non-chassis-connected daughterboards.

Rationale

GND_CHASSIS exists to bond a PCB to the metal enclosure for EMC shielding, ESD protection, and safety earth. None of those functions apply to the JDB because:

No chassis surface — the JDB is an internal daughterboard that floats above the Controller board on hat-header pins and conductive standoffs. It has no metal enclosure surface it can directly bond to.
EMC envelope already provided — the Controller board beneath it carries a correctly implemented GND_CHASSIS net bonded to the system enclosure. The JDB sits entirely within that envelope.
No external connections — the JDB has no cables or connectors that exit the enclosure, so there are no ESD entry points that would require chassis bonding at the JDB level.
Low-EMI device — the FT232H operates at USB 2.0 speeds on an internal point-to-point link. It generates no significant conducted or radiated emissions that would require additional chassis shielding.
Daisy-chaining adds no value — connecting JDB GND_CHASSIS via standoffs to Controller GND_CHASSIS would create an additional path to chassis earth but no new bond point, adding PCB complexity for zero measurable EMC benefit.

Implementation

Include mounting holes on the JDB for mechanical stability.
Standoffs are conductive (metal); this incidentally bonds the JDB mounting hole copper pours to the Controller board mechanically.
Mounting hole copper pours connect to GND (circuit return) — not to a separate GND_CHASSIS net.
This is consistent with standard practice for small internal sub-modules (e.g. Arduino shields, FPGA daughter cards).

Alternatives Considered

Standoff bonding to Controller GND_CHASSIS: Technically implementable but adds a separate net, a copper pour, and design rules for no measurable EMC gain on a low-EMI internal board. Rejected.
No mounting holes at all: Rejected — mechanical retention via standoffs is required to prevent the board from flexing on the hat-headers during connector insertion/removal.

DEC-024 — JDB is Complete JTAG Master; Controller JTAG Lines Are Pass-Through

Status: Decided
Date: 2026-04-06
Category: Electrical
Area: JTAG Architecture — Controller and JTAG Daughterboard

Decision

The JTAG Daughterboard (JDB) is the complete JTAG master. The SN74LVC2G125DCUR dual-channel buffer (U5) for TCK and TMS, and all 33 Ω series damping resistors (R6 TCK after U5, R7 TMS after U5, R8 TDI direct from FT232H) are located on the JDB, before the J2 JTAG header. The Controller board routes JTAG lines (TCK, TMS, TDI, TTD_RETURN, VREF) as pass-through from the JDB hat-header to the LINK-BETA BtB connector without any active components.

LINK-BETA is a direct Board-to-Board connector (no cable). Therefore 33 Ω series damping (matched to 50 Ω PCB trace impedance) applies throughout — not the 75 Ω cable-driving resistors specified for ribbon cable connections. See DEC-016 for the full 75 Ω / 33 Ω rationale.

Rationale

Simpler Controller BOM: Removing U5, R4, R5, R6 from the Controller reduces complexity and potential assembly errors on the main board.
Cohesive JTAG subsystem: All JTAG active components and termination are co-located on the JDB, which is the natural owner of the JTAG function.
BtB confirmation: LINK-BETA is a Samtec ERF8-020 / ERM8-020 direct board-to-board stack (no ribbon cable). The 33 Ω source termination after U5 is the correct value for 50 Ω PCB traces.

Impact

Controller/Design_Spec.md: U5 removed from BOM; R4, R5, R6 removed; §3 updated to reflect pass-through routing; DR-CTL-05 updated; FR-CTL-04 reference to U5 removed.
JTAG_Daughterboard/Design_Spec.md: U5 added to BOM; R6, R7, R8 (33 Ω 0402) added.
Electronics/Consolidated_BOM.md: SN74LVC2G125DCUR moved from CTL column to JDB column; 33 Ω 0402 count increased in JDB; 33 Ω 0603 row removed from CTL.
Electronics/Investigations/JTAG_Integrity.md: §7.4 and §8 updated to reflect JDB location.
Design_Log.md DEC-016: Update note added.

DEC-025 — CM5 Shutdown Mechanism: Interrupt-Driven via Custom Linux Driver (Deferred)

Status: Deferred — Software PoC Stage
Date: 2026-04-09
Category: Software
Area: Software / Linux OS — CM5 Power Management Shutdown Path

Decision

The final implementation of the CM5 graceful shutdown mechanism — triggered by the LTC3350 BACKUP signal — is deferred to the Software PoC stage, pending hardware availability for integration testing. The real implementation will use a custom Linux kernel driver that registers the BACKUP signal as a hardware interrupt, rather than a userspace polling daemon.

The PWR_GD GPIO (GPIO 27, MCP121T-450E output) is rail-health telemetry only and does NOT trigger shutdown. It is a CM5 input that reads HIGH while 5V_MAIN ≥ 4.50V.

Rationale

The custom driver approach eliminates polling latency entirely (interrupt response is effectively immediate vs. up to 500 ms for a 2 Hz poll cycle).
Driver development requires the physical hardware to be available for testing and validation. Writing and verifying kernel interrupt handlers against simulated hardware is impractical.
The system is designed for operational sessions of 15–30 minutes or longer. The hold-up window (≥33.5 s) is a generous safety margin; an unplanned shutdown from a fully-charged state is expected to be harmless. Deferring the driver to the PoC stage does not create a risk for hardware bring-up.
Placeholder pseudocode in design/Software/Linux_OS/Power_Management.md documents the intended behaviour for reference; it is not a specification.

Impact

design/Software/Linux_OS/Power_Management.md Phase 1: Polling daemon pseudocode replaced with deferred-decision note referencing DEC-025. The active hardware protection path is the LTC3350 /INTB → MIC1555 U15 → Q5 BSS138 → PWR_BUT one-shot circuit (3.01 s LOW pulse), which requires no software driver.

DEC-026 — Rotor Position Encoder: AS5600 Replaced with Single-Track Capacitive Encoder

⚠️ Partially superseded by DEC-028 for dual-track N=64 architecture, Ø92mm PCB diameter, and aluminium shroud milled slots. Retained for historical context.

Status: Accepted
Date: 2026-04-12
Category: Hardware
Area: Rotor Board — Position Sensing (§2.1)

Decision

The AMS AS5600 magnetic encoder (originally specified in DR-ROT-03) is replaced with a single-track absolute capacitive encoder implemented entirely on the rotor PCB. The rotating shroud flanges carry milled aluminium slots (air gap = low capacitance); K capacitive sensor pads on the PCB read the track as a K-bit code. A combinational lookup table in the CPLD VHDL maps the raw sensor code to a binary rotor position (0 to N−1). The SW1 modulo-N adder (ring setting) operates on the decoded binary value. No external adder hardware is required — the decode and add are pure CPLD logic.

Two Texas Instruments FDC2114RGHR (4-channel, I²C, 16-VQFN, 3.3V) per rotor replace U2:

U2 (address 0x2A): Track A — bits[5:3] (N=64) or STGC bits[3:0] (N=26).
U3 (address 0x2B): Track B — bits[2:0] (N=64 only). NOT POPULATED for N=26. See U4 on Board A for N=26 bit[4].
CPLD implements I²C master to read pad states.

Track patterns (verified — all N codes unique)

26-char (K=5, N=26): 00000100011001010011101111 Sensors at 0°, 13.846°, 27.692°, 41.538°, 55.385° from reference; arc/segment ≈ 10.63mm at r=44mm. Invalid codes (between-character / jam): 11, 13, 21, 22, 26, 31.
64-char (K=6, N=64): Replaced by dual-track 3+3 reflected binary Gray code — see Rotor_64_Char_Design.md §7 and DEC-028. Sensors at 0°, 5.625°, 11.25°, 16.875°, 22.5°, 28.125° from reference; arc/segment ≈ 4.32mm at r=44mm. All 64 six-bit codes are valid (standard 6-bit reflected binary Gray code; XOR-chain decode; no invalid-code jam detection required).

PCB outer diameter Ø92mm (inside Ø100mm aluminium shroud) — per DEC-028

Rationale

AS5600 incompatible with single-track Gray code intent: AS5600 is a single-magnet absolute angle sensor — it requires a single magnet on the rotating part and returns a 12-bit angle value. It does not implement Gray code sensing and was architecturally inconsistent with the original design intent stated in §1 ("single-track grey encoder").
No magnet pocket on shroud: The AS5600 requires a diametrically magnetised magnet (~6mm dia) embedded in or attached to the rotating shroud, adding manufacturing complexity. The capacitive approach requires only milled aluminium slot patterns on the rotating shroud — no embedded components.
All sensing electronics on PCB: Capacitive pads and FDC2114 ICs are standard PCB components. The shroud is a passive mechanical part.
Reliable at slow rotation rates: The rotors step at human-typing speed (≤10 char/s). The FDC2114 conversion time (~1ms/channel at default rate) is well within the inter-step interval.
STGC lookup table consistent across variants: Both 26-char and 64-char rotors use the identical CPLD decode mechanism; only table contents and modulus differ. No firmware architecture difference between variants.

Impact

design/Electronics/Rotor/Design_Spec.md: FR-ROT-02, FR-ROT-08, DR-ROT-03, DR-ROT-09, §1, §2.1 (full rewrite), §3.2 I²C note, BOM U2 → FDC2114RGHR, U3 added.
design/Electronics/Rotor/Rotor_26_Char_Design.md: §5 ring setting updated; §6 added (geometry, track pattern, STGC→position lookup table).
design/Electronics/Rotor/Rotor_64_Char_Design.md: §5 ring setting updated; §7 added (geometry, track pattern, STGC→position lookup table).
design/Electronics/Rotor/Board_Layout.md: ASCII diagram updated; PCB Ø92mm (per DEC-028).
design/Electronics/Consolidated_BOM.md: AS5600 row replaced with 2× FDC2114RGHR per rotor (60 units total across 30 rotors).
design/Electronics/Reflector/STGC_Generator.py: Original script location noted — should be relocated to design/Electronics/Rotor/ in a future tidy-up commit.

DEC-027 — Rotor Position Readback via JTAG Virtual JTAG (USER0 UDR)

Status: Accepted
Date: 2026-04-12
Category: Hardware / Firmware
Area: Rotor Board CPLD — JTAG Interface; GUI App position display

Decision

The CPLD on each rotor must expose the effective rotor position (STGC-decoded position + SW1 ring offset, mod N) via Intel Virtual JTAG (Altera VIRTUAL_JTAG megafunction, USER0 instruction) over the existing JTAG serial chain. This allows the CM5/JDB to read back all 30 rotor positions in a single JTAG scan pass without consuming any additional PCB pins or signal routing.

The effective position register is 6 bits wide (covers both variants; 26-char variant uses bits [4:0], bit [5] = 0). The CPLD VHDL must instantiate the VIRTUAL_JTAG megafunction and connect the effective position register to the user data register (UDR). Cipher substitution operates continuously and independently of JTAG state.

Rationale

Standard IEEE 1149.1 BSCAN cannot access internal registers: Boundary scan (EXTEST/SAMPLE) captures I/O pin states only. The effective position is an internal CPLD register result and would require dedicated output pins to be visible via standard BSCAN.
Virtual JTAG avoids pin consumption: The existing JTAG chain (TCK, TMS, TDI, TDO/TTD) is already routed through all 30 rotors. No additional pins, traces, or connectors are needed.
FT232H on JDB supports arbitrary JTAG instructions: The JDB FT232H (in MPSSE mode) can issue the USER0 JTAG instruction to any device in the chain and clock out the UDR contents. The CM5 software can therefore poll all 30 positions by iterating through the chain.
GUI App feedback requires position data: The GUI App Design_Spec requires real-time display of rotor positions. Virtual JTAG is the only defined data path from rotor CPLDs to the CM5 for this purpose — no I²C, SPI, or dedicated signal lines exist between the rotors and the CM5.
Non-intrusive to cipher operation: The VIRTUAL_JTAG megafunction is fully synchronous with the JTAG clock domain and does not gate or interrupt the cipher substitution logic running on the CPLD system clock.

Impact

design/Electronics/Rotor/Design_Spec.md: FR-ROT-09 to be added (CPLD exposes effective position via JTAG USER0 UDR; 6-bit register; readable without interrupting cipher function). Note to be added in §2.2 or §3.3 cross-referencing Virtual JTAG and GUI App.
design/Software/GUI_App/Design_Spec.md: Cross-reference to DEC-027 and JTAG readback path to be added when GUI App position-display feature is specified.
CPLD VHDL (future): Must instantiate VIRTUAL_JTAG megafunction and connect effective position register. Scan sequence: JDB issues USER0; shifts 6-bit UDR from each of 30 rotors serially (180 bits total per full scan).
design/Electronics/JTAG_Daughterboard/Design_Spec.md: FT232H MPSSE mode already specified; no hardware change required. Software driver must add USER0 scan sequence.

DEC-028 — Split dual-board rotor architecture

Status: Accepted
Date: 2026-04-14
Category: Hardware
Area: Rotor Board — Physical Architecture; PCB Assembly; Position Encoder

Decision

The rotor is split into two circular PCBs (Board A input side, Board B output side), each Ø92mm, connected by four single-row 2.54mm THT headers (H_SW3 1×7, H_PWR 1×5, H_JTAG 1×5, H_SENS 1×5; 22 pins total; mixed gender for physical keying). This resolves the JLCPCB single-side SMT assembly constraint and simultaneously defines the rotor physical thickness (~15mm with an 11.8mm board gap). Board A carries the CPLD (U1 EPM570T100I5N), FDC2114 U2 (Track A encoder, bits[5:3] for N=64 or all 5 sensors for N=26), SW1 (ring setting DIP), SW2 (forward map select DIP), and J1–J3 (ERM8 male, input side). Board B carries FDC2114 U3 (Track B, bits[2:0], N=64 only — not populated for N=26), SW3 (return map select DIP), and J4–J6 (ERF8 female, output side). These internal headers are manually assembled post-JLCPCB SMT pick-and-place.

The aluminium shroud (Ø100mm outer, 4mm radial wall → Ø92mm inner) floats electrically, retained by rolling-pin style cylindrical bearings with ceramic or nylon rolling elements for electrical isolation. Gray code position slots are milled into the inner faces of the shroud flanges (dish side for Track A / Board A; cover side for Track B / Board B). Bare copper electrode pads on the PCB flat face at r≈44mm sense the pattern capacitively via FDC2114.

For N=64 the encoder is a dual-track 3+3 bit standard reflected Gray code (6-bit), giving zero multi-bit transitions including wrap-around (position 63→0). The CPLD decodes via XOR chain (G2B). For N=26 all 5 STGC sensor electrodes remain on Board A; U3 on Board B is not populated.

Rationale

JLCPCB only performs SMT assembly on one side per PCB; splitting the board places all SMT components on the outward-facing side of each board, making both boards fully JLCPCB assemblable without manual rework of back-side SMT.
The ~15mm rotor thickness matches original Enigma rotor proportions.
The split enables a dual-track capacitive encoder (3+3 bits), achieving a perfect 6-bit reflected Gray code for N=64 with zero multi-bit transitions at any rotor position including the 63→0 wrap. This replaces the de Bruijn STGC approach (which required a lookup table and had no wrap-around guarantee).
The aluminium shroud is passive: no conductive ink, no embedded magnets. Gray code slots are milled CNC features on a standard turned-aluminium part. Bearing isolation keeps the shroud electrically floating, preventing ground loops and capacitive coupling errors.

Alternatives Considered

Single-board with back-side hand-soldering: rejected — complex, unreliable, not consistent with high-volume JLCPCB assembly.
Magnetic encoder on shroud: rejected — adds active or passive magnetic components to the shroud, increasing mechanical complexity and cost.
Optical encoder: rejected — requires more complex shroud features (apertures or reflective strips) and additional LED/photodiode components on the PCB inner face.

Impact

design/Electronics/Rotor/Design_Spec.md: §1 (two-board architecture, Ø92mm PCBs, shroud description), §2.1 (rewritten for capacitive encoder with milled shroud flanges), §3.4 (J_INT internal headers H_SW3/H_PWR/H_JTAG/H_SENS added), BOM split into Board A / Board B, FR/DR updated.
design/Electronics/Rotor/Board_Layout.md: rewritten for Board A and Board B with stacking cross-section; all Ø100mm references updated to Ø92mm.
design/Electronics/Rotor/Rotor_64_Char_Design.md: de Bruijn track replaced by 3+3 dual-track reflected Gray code; XOR-chain decode; geometry updated to r=44mm / Ø92mm.
design/Electronics/Rotor/Rotor_26_Char_Design.md: single-track all-on-Board-A confirmed; geometry updated to r=44mm / Ø92mm; U3 not-populated note added.
design/Electronics/Consolidated_BOM.md: J_INT internal headers (H_SW3 PH1-07-UA/RS1-07-G, H_PWR PH1-05-UA/RS1-05-G, H_JTAG PH1-05-UA/RS1-05-G, H_SENS PH1-05-UA/RS1-05-G) added, 4 headers per rotor assembly (120 total for 30 rotors).

DEC-029 — Supercapacitor Hold-Up Specification: 25F Abracon Cells, 2S4P, ≥20 s at 15W

Status: Accepted — 2026-04-14
Date: 2026-04-14
Category: Electrical
Area: Power Module — Supercap Bank, Hold-up Specification
Supersedes: DEC-004 (cell reference), DEC-021 (cell capacitance and count)
References: DR-PM-07, DR-PM-09, BOM C_SC1–8

Decision

The supercapacitor hold-up minimum requirement is ≥20 seconds at a 15W shutdown load (CM5 typical operating current: 5V × 3A = 15W). The confirmed cell selection (Abracon ADCR-T02R7SA256MB, 25F/2.7V) in a 2S4P (8-cell) arrangement provides ≥33.5 seconds.

⚠️ Cell lock: Cells are Abracon ADCR-T02R7SA256MB, 25F/2.7V in 2S4P (8 cells). Stale values 22F, 33F, 37.5F, 21.7 s, and 24.8 s must never reappear. Any proposed cell or configuration change requires recalculating hold-up against the ≥20 s rule below using the 15W load figure.

Correct Load Figure

⚠️ The CM5 draws 5V × 3A = 15W during typical operation. When a power-loss event occurs, the CM5 is running at this load and continues to draw it throughout the OS shutdown sequence (~10–15 s). Earlier documents used 5W (1A) which significantly overstated margin. All hold-up calculations must use 15W as the minimum design load.

Configuration

Parameter	Value
Cell part number	Abracon ADCR-T02R7SA256MB
Cell capacitance	25F / 2.7V each
Configuration	2S4P — 8 cells total (C_SC1–C_SC8)
Effective capacitance	50F at 5.4V
Charge voltage (2S)	5.4V
Block footprint	37mm × 77mm (2 columns × 4 rows, 20mm pitch)
Shadow zone	41mm × 81mm

Hold-Up Calculation

Usable energy from a capacitor bank discharged from V_hi to V_lo:

E = ½ × C × (V_hi² − V_lo²)

Load power during shutdown: P = 15W (CM5 at 5V × 3A typical).

Hold-up duration: t = E × η / P

Conservative model (pure-buck — LTC3350 loses regulation at V_lo ≈ 4.75V)

Step	Calculation	Result
Usable energy	½ × 50 × (5.4² − 4.75²)	164.9J
Hold-up @ 15W	164.9J / 15W	11.0 s ❌

This model is unrealistic — the LTC3350 is a 4-switch synchronous buck-boost, not a simple buck. It is shown here only to illustrate that relying on the cap voltage staying above the output voltage is not sufficient at this load.

Realistic model (LTC3350 boost mode, V_lo = 2.0V, η = 80%)

The LTC3350 actively boosts the supercap voltage to maintain 5V output in backup mode. Minimum practical V_CAP of ~2.0V protects cells from over-discharge (1.0V/cell for 2S).

Step	Calculation	Result
Stored energy (V_lo = 2.0V)	½ × 50 × (5.4² − 2.0²)	629J
Delivered (η = 80%)	629J × 0.80	503J
Hold-up @ 15W	503J / 15W	≥33.5 s ✅

Sensitivity to LTC3350 efficiency at 15W load

Efficiency	Delivered energy	Hold-up	Pass ≥20 s?
85%	535J	35.6 s	✅
80%	503J	33.5 s	✅
75%	472J	31.5 s	✅
67%	421J	28.1 s	✅
48% (minimum)	302J	20.1 s	✅ (edge)

The ≥20 s rule is satisfied even if converter efficiency degrades to ~48%, which is far below any credible operating point for a synchronous buck-boost at these voltages and currents.

Rationale

Why 2S4P (8 cells) and not 2S3P (6 cells)? At 15W, 2S3P (37.5F) delivers 377J at 80% efficiency → 25.2 s. This passes the 20 s rule but leaves only 26% margin. 2S4P (50F) delivers 503J → 33.5 s, a 68% margin, providing meaningful headroom against LTC3350 efficiency variation, higher CM5 loads during bring-up, and supercap aging.
Why 15W? The CM5 module draws 5V × 3A under typical operating load. When power is lost, the OS shutdown sequence takes ~10–15 s during which the CM5 continues at near-full load. Using 5W (1A) as the design load significantly understates the required hold-up margin and was an error in DEC-004 and DEC-021.
0.5A PoE charge current (from DEC-004) retained: charge power = 5.4V × 0.5A = 2.7W, unaffected by the cell count increase. Charge time from fully depleted ≈ 9 minutes (100F per series position × 2.7V / 0.5A = 540 s). PoE utilisation calculations in Certification_Evidence are unaffected.

Constraints

Do not change the cell MPN, cell count, or configuration without re-running the hold-up calculation at 15W against the ≥20 s rule and updating DR-PM-07, DR-PM-09, and this DEC.
LTC3350 CELLS register must remain configured for 2 series cells (CELLS = 0x01).
PCB shadow zone: 41mm × 81mm. No traces on L1–L6 within this zone (enclosure rib clearway).

DEC-030 — 5V_MAIN Backup Switchover Transient Fix (R14, R30, C35)

Status: Accepted
Date: 2026-04-14
Category: Electrical
Area: Power Module — LTC3350 Backup Switchover, 5V_MAIN Bulk Capacitance

Issue

At 3A load (CM5 typical draw), the existing 5V_MAIN bulk capacitance (C9=22µF + C10=22µF + C13=10µF = 54µF total) provides only 2.59µs before PWR_GD deasserts (54µF × 144mV / 3A). The LTC3350 at default 200kHz (5µs/cycle) gets only 0.52 cycles to complete backup switchover — INSUFFICIENT.

Root Cause Analysis

Old R14 = 28.7kΩ → backup threshold = 4.644V; PWR_GD deassert = 4.50V; gap = 144mV
LTC3350 RT=INTVCC (no resistor) = 200kHz → 5µs/cycle
54µF × 144mV / 3A = 2.59µs = 0.52 cycles → FAILS

Fix (three combined changes)

R14: 28.7kΩ → 30.1kΩ — raises backup threshold to 4.812V; new gap = 312mV
R30: new 33.2kΩ resistor (LTC3350 RT pin to GND) — sets switching frequency to 400kHz (2.5µs/cycle)
C35: 2× Samsung CL32B226KAJNNNE (22µF 25V X7R 1210) in parallel = 44µF additional bulk on 5V_MAIN

Result with Fix

Total bulk = 54µF + 44µF = 98µF
Time window = 98µF × 312mV / 3A = 10.2µs
Cycles at 400kHz = 10.2µs / 2.5µs = 4.1 cycles ✓
False-trigger headroom: 5V×0.98 − 4.812V = 88mV (LTC3350 ~12µs deglitch filters brief dips)

Component Selection Rationale for C35

Selected: 2× Samsung CL32B226KAJNNNE (22µF 25V X7R 1210, existing BOM part)
- ESR ≈ 10mΩ (negligible, stable −55°C to +125°C)
- Uses existing qualified BOM part — no new component qualification needed
- 4.1 cycles margin at all operating temperatures
Evaluated and rejected: HZA107M025X16T-F (CDE hybrid polymer-Al, 30mΩ ESR, 4.56 cycles at +20°C but marginal 2.1 cycles at −40°C — not selected as existing BOM part is sufficient)
Evaluated and rejected: KEMET T495X107K025ATA150 (MnO₂ tantalum, 150mΩ ESR — V_ESR = 450mV at 3A, EXCEEDS entire 312mV budget; also MnO₂ tantalum short-circuit failure mode is unsafe in low-impedance power supply)

No Change Required To

eFuse (HV input side)
LDO TPS75733 (stays in regulation)
MIC1555/R28/C32 (3.01s timing unchanged)

DEC-031 — CM5 Virtual Keyboard (Key Injection) Feature Architecture

Status: Decided
Date: 2026-04-14
Category: Electrical / Firmware
Area: Stator Board — I²C Expanders, Servo, CPLD SOURCE_SEL MUX
Author: Izzyonstage & GitHub Copilot

Summary

Design decision for enabling the CM5 to autonomously inject virtual keypresses into the Enigma cipher pipeline, enabling automated rotor configuration testing and fully autonomous cipher operation.

Problem

The Enigma machine requires a physical keypress to advance rotors and inject input into the cipher pipeline. For autonomous CM5 operation (testing, remote cipher operation), a mechanism is needed to inject keypresses without human intervention.

Decision

Add three I²C expanders to the Stator board on the shared I²C-1 bus:

MCP23017 @ 0x20 (U_EXP1): 16-bit GPIO expander for ENC_IN/ENC_OUT monitoring. Replaces CM5 GPIO 4–15 (12 pins freed).
- GPA[0:5] = ENC_IN[0:5] monitor (inputs)
- GPB[0:5] = ENC_OUT[0:5] monitor (inputs)
- GPA[6:7], GPB[6:7] = spare
MCP23017 @ 0x21 (U_EXP2): 16-bit GPIO expander for virtual keypress injection, SOURCE_SEL MUX control, SYS_RESET_N (replaces CM5 GPIO 26 — 1 pin freed), servo enable, and SERVO_HOME sense.
- GPA[0:4] = KEY_ADDR[0:4] (outputs — 5-bit key address to Stator CPLD)
- GPA[5] = KEY_EN (output — enable for virtual keypress injection)
- GPA[6] = SOURCE_SEL (output — MUX select: 0=keyboard, 1=CM5 virtual)
- GPA[7] = SYS_RESET_N (output — system-wide CPLD reset)
- GPB[0] = SERVO_EN (output — enables servo PWM output)
- GPB[1] = SERVO_HOME (input — active-low homing switch, 10kΩ pull-up + 100nF debounce)
- GPB[2:7] = spare
PCA9685 @ 0x60 (U_EXP3): 16-channel I²C PWM driver for servo motor control.
- Ch0 = SERVO_PWM (50Hz PWM for servo position control)
- A5 → 3V3_ENIG (sets bit 5 = 1), A4–A0 → GND (bits 4:0 = 0) → address 0x60
- All-call address (0x70) disabled in enigma daemon init (MODE1 reg bit 0 = 0)

Rationale for MCP23017 (×2)

32 GPIO total provides headroom for future I/O expansion.
SYS_RESET_N migration to expander reduces LINK-BETA pin count and frees CM5 GPIO 26.
All monitoring and control signals consolidated on Stator (co-located with servo and CPLD).
Only 2 wires (I²C SDA/SCL) needed on LINK-BETA instead of 13 discrete signal pins.

Rationale for PCA9685 @ 0x60

MCP23017 cannot generate PWM; a dedicated PWM IC is required for servo control.
Address 0x60 chosen (not 0x40 base) for I²C debugging clarity — all peripheral ICs sit at lower addresses; the expander group starts at 0x60.
A5=HIGH, A4–A0=LOW wiring achieves 0x60.
All-call address 0x70 disabled in enigma daemon init (MODE1 register bit 0 = 0).

Servo Motor

Part: Miuzei Metal Gearbox 90 servo (purchased — Amazon, 6 for $18, geekpow seller).
Voltage: 4.8–6V rated; powered from 5V_MAIN (within spec).
Actuation cycle: 0°→180°→0° sweep = one virtual keypress.
Mounted: on Stator PCB via J_SERVO (3-pin JST PH 2.0mm: 5V_MAIN, GND, SERVO_PWM).

SERVO_HOME Switch

SPST normally-open momentary switch, active-low.
Mounted on Stator PCB.
10kΩ pull-up to 3V3_ENIG + 100nF X7R cap to GND (RC τ = 1ms).
Connected to MCP23017 U_EXP2 GPB[1].
Homing sequence: assert SERVO_EN → command 0° → poll SERVO_HOME LOW within 3-second timeout.

SOURCE_SEL MUX

GPA[6] on U_EXP2 drives Stator CPLD SOURCE_SEL input at J4 ENC_OUT[0:5] entry point.
SOURCE_SEL=0: keyboard ENC_OUT is forwarded to the encryption pipeline.
SOURCE_SEL=1: KEY_ADDR[0:4] + KEY_EN from U_EXP2 GPA[0:5] synthesises a virtual ENC_OUT signal.

Net Effect on LINK-BETA

Freed (13 pins): ENC_IN[0:5] (×6), ENC_OUT[0:5] (×6), SYS_RESET_N (×1).
Freed: pins 8 (SYS_RESET_N), 12–17 (ENC_IN[0:5]), and 19–24 (ENC_OUT[0:5]) were freed by this decision.
Later reuse: DEC-036 reallocated the former monitor block into grouped LINK-BETA power rails (5V_MAIN, 3V3_ENIG, and GND) once the Stator-side 5V needs were formalised.
R6 pull-up (10kΩ to 3V3_ENIG) on Stator keeps SYS_RESET_N HIGH at power-up (CPLDs out of reset).

Net Effect on CM5 GPIO

Freed (13 pins): GPIO 4–15 (ENC monitoring), GPIO 26 (SYS_RESET_N).
No new CM5 GPIO assignments required.

I²C Bus Address Map (no conflicts)

Address	Device	Location
0x09	LTC3350	Power Module
0x0B	Smart Battery	Power Module
0x20	MCP23017 (U_EXP1)	Stator
0x21	MCP23017 (U_EXP2)	Stator
0x22	MCP23017 (U_EXP4)	Stator
0x23	MCP23017 (U_EXP_SW_IN)	Settings Board
0x24	MCP23017 (U_LED_B1)	Settings Board
0x25	MCP23017 (U_LED_B2)	Settings Board
0x28	STUSB4500	Power Module
0x40	INA219 (U12)	Power Module
0x45	INA219 (U2)	Stator
0x60	PCA9685 (U_EXP3)	Stator

DEC-032 — Settings Board: Panel-Mount Illuminated Configuration Switches with CM5 Override

Status: Decided
Date: 2026-04-14
Category: Electrical / HMI
Area: Stator Board — Configuration Interface; new Settings Board PCB
Author: Izzyonstage & GitHub Copilot

Summary

Replace the Stator Board's DIP switches (SW1 routing, SW2 reflector map) with panel-mount toggle switches plus discrete RGB indicators on a dedicated Settings Board PCB. The Settings Board connects to the Stator via I²C only (no parallel signal wiring). A new MCP23017 expander (U_EXP4 @ 0x22) on the Stator Board bridges the I²C configuration data to the CPLD config input pins.

Problem

The Stator's DIP switches (SW1, SW2) are internal PCB components, requiring the enclosure to be opened to change the routing or reflector map configuration. This is inconvenient for regular use. Additionally, the CM5 has no way to programmatically override the configuration.

Decision

Remove SW1 and SW2 from the Stator Board.
Add a new Settings Board PCB (panel-mount, right side of enclosure top face near rotors) with:
- 12 panel toggle switches plus 12 discrete RGB indicators (5 for Bank 1 routing, 7 for Bank 2 reflector mapping)
- 1 momentary CFG_APPLY input; a board-mounted tactile switch actuated through the enclosure is acceptable
- U_EXP_SW_IN (MCP23017 @ 0x23): reads switch states
- U_LED_B1 (MCP23017 @ 0x24): drives Bank 1 LED anodes + Bank 1 colour rails
- U_LED_B2 (MCP23017 @ 0x25): drives Bank 2 LED anodes + Bank 2 colour rails
Add U_EXP4 (MCP23017 @ 0x22) to the Stator Board. Its outputs drive the CPLD configuration input pins directly (SW1[0:3] and SW2[0:5]). Pull-downs R16–R26 are retained on the CPLD input pins to hold safe defaults (all-zero) at power-up before CM5 initialises U_EXP4.
CM5 firmware (enigma daemon):
- Reads U_EXP_SW_IN to get physical switch state
- If bank enable HIGH (switch-defined): writes switch values to U_EXP4, drives LED colour green
- If bank enable LOW (CM5-defined): CM5 writes its own config to U_EXP4, drives LED colour red
- After writing final config to U_EXP4, pulses STATOR_CFG_RDY (U_EXP4 GPA[4]) LOW→HIGH to trigger CPLD re-latch of new configuration
Physical CFG_APPLY button on Settings Board: reads via U_EXP_SW_IN GPB[7]; CM5 daemon polls this and triggers the same U_EXP4 write + STATOR_CFG_RDY strobe when pressed. The switch may be a board-mounted tactile part with a simple actuator/plunger through the enclosure rather than a true panel-mount pushbutton.

LED Colour Scheme

Green illumination: Bank is in switch-defined mode (bank enable HIGH); illuminated bits show active switch positions.
Red illumination: Bank is in CM5-defined mode (bank enable LOW); illuminated bits show CM5-programmed configuration.
Per-bank shared colour rail: all switches in a bank share the same colour (green or red) while individual anode control shows which bits are set.

I²C Address Assignments (new)

Address	Device	Location
0x22	MCP23017 (U_EXP4)	Stator — CPLD config output driver
0x23	MCP23017 (U_EXP_SW_IN)	Settings Board — switch input reader
0x24	MCP23017 (U_LED_B1)	Settings Board — Bank 1 LED anode + colour rail driver
0x25	MCP23017 (U_LED_B2)	Settings Board — Bank 2 LED anode + colour rail driver

Rationale

Replacing DIP switches with panel toggles makes configuration user-accessible without opening the enclosure.
I²C-centric wiring between Settings Board and Stator keeps the cable harness minimal vs 10+ parallel signal wires; the active harness is now a 6-wire JST PH link carrying 3V3_ENIG, 5V_MAIN, GND, SDA, SCL, and a dedicated LED return GND.
Retaining R16–R26 pull-downs ensures the CPLD receives a safe all-zero default at power-up (no plugboard insertion, physical reflector pass-through) before the CM5 writes the desired config.
Per-bank enable switches give the operator independent control of whether the physical switches or CM5 firmware define each bank's configuration.
RGB illumination (green/red) provides immediate visual feedback on configuration source with no additional UI required.

Supersession note: This decision records the original Settings Board migration intent. The active address map and harness definition were later refined by the post-audit cleanup: U_EXP_SW_IN @ 0x23, U_LED_B1 @ 0x24, U_LED_B2 @ 0x25, and a 6-wire JST PH harness carrying 3V3_ENIG, 5V_MAIN, GND, SDA, SCL, GND.

Impact

Stator Board: SW1 and SW2 removed; U_EXP4 and J_CFG added; STATOR_CFG_RDY signal added to CPLD
New Board: Settings Board added to system BOM
Firmware: enigma daemon startup sequence must: read U_EXP_SW_IN, evaluate bank enables, write U_EXP4, pulse STATOR_CFG_RDY, update U_LED_B1 / U_LED_B2
CPLD: STATOR_CFG_RDY is a new input pin; CPLD must re-latch SW1/SW2 values on rising edge (replaces power-up-only latch)

DEC-033 — DSI1 Display Connector Provision for Optional Lid Touchscreen

Status: Decided
Date: 2026-04-14
Category: Electrical / HMI
Area: Controller Board — CM5 display interface; Main Enclosure lid
Author: Izzyonstage & GitHub Copilot

Summary

Add a DSI1 4-lane FPC connector (J_DSI1) to the Controller Board to provision for an optional lid-mounted touchscreen display, enabling the Enigma-NG to operate as a self-contained machine without an external monitor. The Display Add-on Board design is deferred.

Problem

The Enigma-NG currently relies on an external HDMI monitor and USB HID devices for system management and GUI display. With the CM5 virtual keyboard injection (DEC-031) and Settings Board (DEC-032) features, the machine is capable of autonomous operation. Adding a lid-mounted touchscreen completes the self-contained package — the only remaining external peripheral would be a keyboard and mouse for system administration tasks.

Decision

Add J_DSI1 (Amphenol F52Q-1A7H1-11015, 15-pin 1.0mm pitch ZIF/FPC connector) to the Controller Board to expose the CM5 DSI1 4-lane interface (CLK +/−, D0–D3 +/−).
Route DSI1 differential pairs on L3 (100 Ω differential stripline — same rule as HDMI/USB). Traces run from CM5 mezzanine connector pins to J_DSI1 near the CM5 socket.
Touch I²C (capacitive touch controller SDA/SCL) is routed via the I²C-1 bus already present on the Controller Board.
J_DSI1 is the only Controller-side display connector fixed in the current scope. Any future display power or auxiliary touch wiring remains deferred with the display add-on board definition.
The HDMI port (J4) is retained and unaffected — J_DSI1 is additive.
Display Add-on Board design (lid mounting frame, FPC cable assembly, backlight driver if required, touch controller interface) is deferred to a future design phase.

Display Interface

Interface: MIPI DSI1 (4-lane)
Differential impedance: 100 Ω (same as HDMI — no new routing rules)
Connector: Amphenol F52Q-1A7H1-11015 — 15-pin 1.0mm pitch right-angle ZIF/FPC
Cable: Thin FPC routed through lid hinge area (far superior to HDMI cable for hinge flexing)
Touch input: Capacitive touch controller I²C on I²C-1 bus (existing bus, no new wires required)
Supported sizes: DSI1 4-lane supports displays up to 10" at full resolution (e.g., RPi official 10" touchscreen)

Rationale

DSI1 FPC cable is thin and flexible — ideal for routing through a lid hinge without fatigue.
Retaining HDMI preserves external monitor compatibility for development and maintenance.
The 100 Ω differential rule is already established on L3 for HDMI — no new stackup or impedance work needed.
Provisioning the connector now (no extra cost, trivial PCB area) avoids a board revision later if the display add-on is adopted.
I²C-1 bus already has spare address space for a touch controller (e.g., FT5426 at 0x38 or similar).

Impact

Controller Board: J_DSI1 added; ~10 new 100 Ω diff traces on L3; small ZIF footprint on L1 near CM5
Main Enclosure: Lid requires provision for display mounting and FPC hinge routing (see Main_Enclosure/Design_Spec.md)
Display Add-on Board: Deferred — to be designed as a separate optional add-on
Firmware / OS: Standard RPi DSI1 display driver; no custom firmware changes needed for basic display output

DEC-034 — Switch Hardware Refresh: Settings Board Toggle + Discrete RGB LED, Ruggedized PM SW1

Status: Decided
Date: 2026-04-16
Category: Electrical / HMI / Mechanical interface
Area: Settings Board; Power Module front-panel switchgear
Author: Izzyonstage & GitHub Copilot

Summary

Replace the old unified Marquardt rocker-switch assumption with two purpose-specific solutions: E-Switch 200-series toggle switches plus discrete RGB LEDs on the Settings Board, and the Adafruit 4660 rugged metal RGB latching switch for Power Module SW1.

Problem

The previous design direction forced the Settings Board and Power Module onto one shared switch family even though the two locations serve different aesthetic, mechanical, and service roles. The Settings Board benefits from classic toggle controls with separate indicators, while the Power Module benefits from a sealed, rugged metal power switch with a more robust panel interface and spade-terminal wiring.

Decision

Settings Board switch selection: Use 200MSP1T2B4M2QE for all 12 configuration toggles (SW_B1_EN, SW_B1[0:3], SW_B2_EN, SW_B2[0:5]).
Settings Board LED selection: Use WP154A4SEJ3VBDZGW/CA for all 12 switch indicators.
- Kingbright 5mm common-anode RGB through-hole LED
- Full RGB operation is available under CM5 control
- Separate red, green, and blue series resistors per switch allow colour balancing under nominal 5V operation
Settings Board LED topology update: Change the indicator drive from the previous common-cathode / PNP sourcing concept to:
- individual LED anode drive from U_LED_B1 / U_LED_B2
- per-bank red / green / blue shared cathode rails
- low-side BSS138 sink devices on each bank colour rail
Power Module switch selection: Use Adafruit 4660 for SW1.
- Latching rugged metal power switch
- RGB ring illumination
- 16mm panel cutout
- 2.8mm pin terminals routed to PCB-mounted 2.8mm male spade tabs for serviceable harnessing

Rationale

The Settings Board now matches the machine's more period-correct control aesthetic better than a rocker-based panel.
Separate LEDs give more freedom over indicator placement and future panel detailing than integrated illuminated switches.
The Power Module switch benefits from a tougher sealed metal body and clearer power-switch identity than the previous shared-family concept.
Breaking the false BOM unification removes a mechanical compromise that was not buying any real electrical simplification.

Impact

Settings Board Design_Spec / Board_Layout: switch type, LED type, and LED driver polarity all change
Consolidated BOM: split the old shared rocker line into distinct Settings Board and Power Module entries
Power Module Design_Spec: SW1 selection and harnessing updated to the rugged metal switch
Copilot handoff / component tracking: the old Marquardt-all-13-switches assumption is retired

DEC-035 — HID Keyboard and Lightboard Use a 40-Position QWERTY-Derived Layout for the 64-Character Code Space

Status: Decided
Date: 2026-04-17
Category: HMI / Mechanical interface / HID logic
Area: HID Assembly; Encoder Board; Rotor actuation interface
Author: Izzyonstage & GitHub Copilot

Summary

Freeze the HID operator interface as a 40-position physical layout rather than a 64-key physical array. The printable positions are [a-z0-9+=], with Left Shift and Right Shift on the bottom row to access uppercase alphabetic codes. The machine still retains its full 64-character logical alphabet.

Problem

Older docs had drifted toward describing the HID assembly as a literal 64-key keyboard, which no longer matched the intended operator experience. That made the purchased keyboard-switch quantity, mechanical lever count, and Encoder input mapping ambiguous, and risked re-introducing separate uppercase-only key positions that were never part of the intended user-facing layout.

Decision

Physical keyboard layout: Use 40 total switch positions in the HID keyboard.
- 26 lowercase alphabetic keycaps: a-z
- 10 numeric keycaps: 0-9
- 2 symbol keycaps: + and =
- 2 modifier keycaps: Left Shift and Right Shift
Logical 64-character repertoire: Preserve the full 64-character code space in Encoder logic.
- Unshifted alphabetic keys emit a-z
- Shifted alphabetic keys emit A-Z
- Digits and + / = are unchanged by Shift
- Therefore the HID path still covers 26 lowercase + 26 uppercase + 10 digits + 2 symbols = 64 unique character codes
Physical lightboard layout: Mirror the same QWERTY-derived printable positions on the lightboard instead of introducing dedicated uppercase-only legends or lamp locations.
Mechanical interface: The rotor actuation mechanism shall therefore be designed around 40 physical key levers, not 64.

Rationale

This matches the intended operator experience of a keyboard-like panel instead of an abstract 64-button matrix.
It preserves the full 64-character cipher alphabet without wasting front-panel area on duplicated uppercase-only key positions.
It aligns the purchased custom keyboard switch count and the HID mechanical packaging with a more realistic enclosure layout.

Impact

HID Assembly Design_Spec: layout, key count, and purchased switch definition fixed at 40 positions
Encoder Design_Spec: HID mapping clarified as 40 physical inputs projected into a 64-code logical space
Rotor Actuation Assembly: lever count reduced from 64 to 40
Consolidated BOM / component tracking: keyboard switch quantity updated to 40 and tied to the pseudo datasheet for the purchased marketplace part

DEC-036 — LINK-BETA Former Monitor Pins Reallocated as Grouped Power Rails

Status: Decided
Date: 2026-04-18
Category: Electrical / Power distribution
Area: Controller Board J2 (LINK-BETA), Stator Board J8, Settings/Servo 5V branch
Author: Izzyonstage & GitHub Copilot

Summary

Keep LINK-BETA as the 40-pin Samtec ERF8/ERM8 pair from DEC-015, but stop carrying a large legacy spare block. Reallocate the former ENC monitor positions into grouped power rails: 4 contiguous 5V_MAIN pins, 3 additional 3V3_ENIG pins, and 3 additional GND return pins.

Problem

After DEC-031 migrated ENC_IN/ENC_OUT monitoring and SYS_RESET_N to Stator-side I²C expanders, a large section of LINK-BETA remained unused. That left the connector under-utilised while the Stator-side 5V branch had only 2 pins (1.0A connector capacity) available for the servo and the Settings Board indicator rail.

Decision

Retain the 40-pin LINK-BETA connector and apply this active allocation:

Pin	Signal	Direction	Notes
1	GND	—	JTAG leading shield
2	TCK	CTRL→Stator	JTAG clock
3	GND	—	TCK/TMS inter-pin shield
4	TMS	CTRL→Stator	JTAG mode select
5	GND	—	TMS/TDI inter-pin shield
6	TDI	CTRL→Stator	JTAG data in
7	GND	—	TDI/GND inter-pin shield
8	GND	—	Extra JTAG trailing/guard ground
9	GND	—	JTAG trailing shield
10	GND	—	Isolation moat pin 1
11	GND	—	Isolation moat pin 2
12	I2C1_SDA	Bidir	Shared Stator/Settings I²C-1 data extension
13	I2C1_SCL	Bidir	Shared Stator/Settings I²C-1 clock extension
14	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
15	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
16	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
17	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
18	GND	—	5V_MAIN return moat
19	3V3_ENIG	PM→Stator	Additional 3V3_ENIG feed
20	3V3_ENIG	PM→Stator	Additional 3V3_ENIG feed
21	3V3_ENIG	PM→Stator	Additional 3V3_ENIG feed
22	GND	—	Grouped return for the mixed-power block
23	GND	—	Grouped return for the mixed-power block
24	GND	—	Grouped return for the mixed-power block
25	GND	—	TTD_RETURN leading shield
26	TTD_RETURN	Stator→CTRL	JTAG TDO short-path return
27	GND	—	TTD_RETURN trailing shield
28–35	3V3_ENIG	PM→Stator	Existing 3V3_ENIG pass-through block
36–40	GND	—	Main power return block

Rationale

The connector footprint, mating safety, and stack geometry from DEC-015 stay unchanged.
Grouping all four 5V_MAIN pins together simplifies routing and clearly separates the 5V branch from the I²C and JTAG regions.
4 × 5V_MAIN pins provide 2.0A connector capacity, giving ample headroom above the current 0.74A downstream budget (Settings Board indicators + servo).
The extra 3V3_ENIG pins make LINK-BETA electrically overprovisioned, so the upstream 3.0A LDO remains the only practical 3V3 limit.

Impact

Controller / Stator LINK-BETA tables updated to grouped 5V_MAIN, 3V3_ENIG, and GND allocations
Settings Board and Stator docs updated to source 5V_MAIN from LINK-BETA pins 14–17
Diagnostic Bank-Beta repurposed from unused spare pads to power/I²C bring-up probes

Cross-ref

DEC-015 (40-pin connector retained). DEC-031 (freed the former monitor pins). DEC-034 (Settings Board full-RGB 5V indicator branch creates a standing Stator-side 5V load).

DEC-037 — LINK-BETA Pin Map Regrouped Around Dedicated JTAG and I2C Guard Bands

Status: Decided
Date: 2026-04-18
Category: Electrical / Interconnect definition
Area: Controller Board J2 (LINK-BETA), Stator Board J8, Controller Bank-Beta diagnostics
Author: Izzyonstage & GitHub Copilot

Summary

Retain the 40-pin LINK-BETA connector from DEC-015, but replace the DEC-036 allocation with a cleaner rail-and-guard arrangement: front power cluster, front 3V3 cluster, dedicated guarded JTAG block, guarded I2C pair, then a rear power cluster. This becomes the only active LINK-BETA pin-definition table.

Problem

DEC-036 solved the spare-pin problem, but the resulting active map split 3V3_ENIG into a small middle block plus a rear block and left the overall pin order harder to reason about in board docs and diagnostics. The design intent now is to preserve a dedicated guarded JTAG region, keep TTD_RETURN near that JTAG region, keep I2C shielded, and make the remaining rails cleaner to read without relying on historical "additional" or "pass-through" distinctions.

Decision

Adopt this LINK-BETA allocation as the active mapping:

Pin	Signal	Direction	Notes
1	GND	—	Front power return / guard
2	GND	—	Front power return / guard
3	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
4	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
5	GND	—	Front power return / guard
6	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
7	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
8	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
9	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
10	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
11	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
12	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
13	GND	—	Front 3V3 return / guard
14	GND	—	Front 3V3 return / guard
15	TCK	CTRL→Stator	JTAG clock
16	GND	—	TCK/TMS guard
17	TMS	CTRL→Stator	JTAG mode select
18	GND	—	TMS/TDI guard
19	TDI	CTRL→Stator	JTAG data in
20	GND	—	TDI/TTD_RETURN guard
21	TTD_RETURN	Stator→CTRL	JTAG TDO short-path return
22	GND	—	TTD_RETURN trailing guard
23	GND	—	JTAG/I2C isolation ground
24	I2C1_SDA	Bidir	Shared Stator/Settings I²C-1 data extension
25	GND	—	SDA/SCL guard
26	I2C1_SCL	Bidir	Shared Stator/Settings I²C-1 clock extension
27	GND	—	I2C/rear-power isolation ground
28	GND	—	Rear power guard
29	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
30	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
31	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
32	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
33	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
34	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
35	3V3_ENIG	PM→Stator	Grouped 3V3_ENIG feed
36	GND	—	Rear 3V3 return / guard
37	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
38	5V_MAIN	PM→Stator	Grouped 5V_MAIN feed
39	GND	—	Rear power return / guard
40	GND	—	Rear power return / guard

Rationale

Preserves a dedicated guarded JTAG block and keeps TTD_RETURN adjacent to the other JTAG nets.
Preserves a separately guarded I2C pair instead of burying it inside a mixed power cluster.
Keeps 4 × 5V_MAIN pins = 2.0A connector capacity, which remains above the current 0.74A downstream Stator-side 5V budget.
Expands LINK-BETA to 14 × 3V3_ENIG pins = 7.0A connector capacity, so the connector remains comfortably above the upstream 3.0A LDO limit.
Removes active-doc wording distinctions like "additional" or "pass-through" from the pin map; the table is now a straightforward interface definition.

Supersession / Obsolescence

DEC-036 is obsolete and retained only as historical traceability for the prior grouped-rail map.
The pin-allocation tables recorded in DEC-015 and DEC-036 are obsolete as active interface definitions; DEC-037 is now the sole authority for LINK-BETA pin placement.
DEC-031 remains valid as the historical migration of SYS_RESET_N and ENC_IN/ENC_OUT off the connector, but it no longer defines the active pin order.

Impact

Controller and Stator LINK-BETA tables updated to the DEC-037 map.
Power-budget docs updated to the new 7.0A LINK-BETA 3V3_ENIG connector capacity.
Stator/Settings power-feed references updated to the new 5V_MAIN pins 3, 4, 37, 38.
Diagnostic Bank-Beta remapped to probe the new LINK-BETA rail and control-pin positions.

Cross-ref

DEC-015 (40-pin connector retained), DEC-031 (functions moved off the connector), DEC-034 (Stator-side 5V indicator load), DEC-036 (obsolete prior grouped-rail map).

DEC-038 — Controller-Centric Dock Architecture Replaces Legacy Link-Alpha / Link-Beta Backplane

Status: Decided
Date: 2026-04-19
Category: Mechanical / Electrical partitioning
Area: Controller Board, Power Module, Stator, system interconnect architecture
Author: Izzyonstage & GitHub Copilot

Summary

Retire the legacy Samtec LINK-ALPHA and LINK-BETA board-to-board model for the Controller ↔ Power Module and Controller ↔ Stator interfaces. The Controller becomes the fixed motherboard and enclosure-edge I/O carrier; the Power Module and Stator become removable daughtercards docked into the Controller.

Problem

The former dual-blind-mate Samtec architecture assumed the Power Module and Stator both attached directly to the Controller through high-pin-count mezzanine connectors. That arrangement no longer matches the enclosure-driven mechanical direction:

the Controller now owns all external I/O placement
the Power Module is a removable power cartridge rather than the I/O edge board
the Stator is a removable vertical daughterboard that must be supported against rotor mass

The old Link-Alpha / Link-Beta definitions also forced low-current Samtec contacts to carry large grouped power allocations and kept obsolete direct PM status GPIOs alive even though a shared I2C-1 bus already reaches the PM.

Decision

1. Controller owns RJ45 / Ethernet / PoE entry

The Controller Board now owns:

RJ45 connector
Ethernet ESD and magnetics handling
PoE PD / ACF front-end
the local cable-entry shield / chassis island for those connectors

The Power Module no longer carries RJ45, Ethernet LED return lines, or GbE MDI routing.

2. Power Module becomes a power-conditioning / UPS cartridge

The Power Module now receives a regulated PoE-derived auxiliary feed from the Controller instead of raw Ethernet-adjacent PoE circuitry. It continues to host:

USB-C PD input
smart-battery input
OR-ing / filtering / eFuse
supercap hold-up
5V_MAIN and 3V3_ENIG generation

3. Controller ↔ Power Module dock is split into three TE connectors

Use three copies of the TE 10-position 2.5 mm board-to-board pair:

Controller side receptacle: 1-1674231-1
Power Module side plug: 1123684-7

Active partition:

Link	Function	Allocation
`J1A`	main regulated rails	`3 × 5V_MAIN`, `2 × 3V3_ENIG`, `5 × GND`
`J1B`	PoE auxiliary handoff	`3 × VIN_POE_12V`, `7 × GND`
`J1C`	low-speed control / telemetry	`I2C1_SDA`, `I2C1_SCL`, `PM_IO_INT_N`, `PWR_GD`, `ROTOR_EN`, `PWR_BUT`, `4 × GND`

4. Controller ↔ Stator dock uses two Molex hybrid connectors

Use the Molex EXTreme Guardian HD pair:

Controller receptacle: 2195630015
Stator plug: 2195620015

Active partition:

5V dock (J2A): 4 × 5V_MAIN power blades, 1 × GND power blade, signal field used as extra GND returns / guards
3V3 / logic dock (J2B): 4 × 3V3_ENIG power blades, 1 × GND power blade, guarded signal field carrying TCK, TMS, TDI, TTD_RETURN, I2C1_SDA, and I2C1_SCL; all remaining signal contacts tied to GND

This retains the JTAG cluster on the 3V3_ENIG / logic-biased connector and gives the Stator two mechanical support points instead of one fine-pitch mezzanine connector.

5. PM-local I2C expander replaces legacy direct PM status GPIOs

Add PCA9534APWR on the Power Module at I2C address 0x3F. Use it for:

inputs: POE_STAT, SYS_FAULT, BATT_PRES_N, USB_STAT
outputs: SW_LED_R, SW_LED_G, SW_LED_B, SW_LED_CTRL

Retain only these direct PM lines:

PWR_BUT
PWR_GD
ROTOR_EN

6. PM RGB sink stage follows the Settings Board pattern

The PM runtime RGB path uses three low-side BSS138 stages with 1kΩ gate resistors and gate pull-down resistors. The pre-boot hardware flash path remains red + green only via Q4 and D6/D7; blue is runtime-only.

7. Grounding rule is unchanged

The only intentional DC bond between GND and GND_CHASSIS remains on the Power Module before the eFuse. The Controller may host local shield/chassis handling for cable-entry hardware, but it must not create a second galvanic bond to system ground.

Rationale

Matches the enclosure-driven mechanical architecture.
Moves high-speed / external I/O ownership to the board that already carries the CM5 and user-facing ports.
Replaces over-loaded fine-pitch Samtec power transport with dock connectors better suited to grouped power.
Keeps PM-local housekeeping close to the PM circuits instead of wasting direct CM5 GPIOs on status lines that already terminate on the PM.
Keeps PM devices clustered in i2cdetect by placing the expander at 0x3F, adjacent to the PM INA219 at 0x40.

Supersession / Obsolescence

DEC-014 is obsolete as an active definition for Controller blind-mate BtB connectors.
DEC-015 and DEC-037 are obsolete as active Controller ↔ Stator interface definitions.
The names Link-Alpha and Link-Beta are retained only for historical traceability in older documents; the active architecture uses J1A/J1B/J1C and J2A/J2B.
Rotor / Extension / Reflector Samtec Edge-Rate connectors are not affected by this decision.

Impact

Controller, Power Module, and Stator design specs must be updated to the new dock model.
Controller PoE / Ethernet ownership moves out of the Power Module docs and BOM ownership.
PM GPIO / SW1 RGB runtime control moves to PCA9534APWR @ 0x3F.
Power-budget and overview documents must stop referencing Samtec Link-Alpha / Link-Beta as active PM/Stator bottlenecks.

Cross-ref

DEC-014, DEC-015, DEC-031, DEC-034, DEC-037.

DEC-039 — Enclosure-Connected Boards Use GND_CHASSIS; Daughterboards Are Exempt

Status: Decided
Date: 2026-04-20
Category: Electrical / EMC
Area: All boards — grounding, mounting, and enclosure bonding
Author: Izzyonstage & GitHub Copilot

Summary

Standardise GND_CHASSIS across the enclosure-connected parts of the system: every enclosure-connected board carries a local GND_CHASSIS net tied to its mounting holes and any deliberate enclosure-contact or shield-contact features, while non-chassis-connected daughterboards are exempt. The only galvanic GND ↔ GND_CHASSIS bond remains on the Power Module at the common power-entry point immediately before the eFuse.

Problem

The prior documentation mixed two different grounding models:

some documents treated GND_CHASSIS as a board-specific feature used only on externally exposed boards
other documents already relied on a shared chassis domain and a single Power Module bond point
JDB-specific wording in DEC-023 needed to remain valid, but the prior update had over-corrected by requiring even non-chassis-connected daughterboards to implement GND_CHASSIS

That ambiguity makes isolated board review harder and risks future designs creating inconsistent mounting-hole grounding or accidental secondary bond points.

Decision

Every enclosure-connected board implements GND_CHASSIS.
- Tie mounting holes and other defined enclosure-contact / shield-contact mechanical features to the local GND_CHASSIS net.
- This applies to removable boards and fixed boards that bond into the enclosure structure.
Non-chassis-connected daughterboards are exempt.
- Board-mounted daughterboards that do not connect directly to the enclosure do not need their own GND_CHASSIS net.
- They are treated as electrical / mechanical extensions of the host board instead.
- The JTAG Daughterboard (JDB) is the canonical example of this exception.
The enclosure is the distributed chassis return path.
- The metal enclosure and bonded mounting hardware form one continuous chassis domain across the machine.
- Transients and shield currents are intended to flow through that chassis domain toward the single galvanic bond instead of being dumped into local logic/power GND on intermediate boards.
Only the Power Module may bond GND to GND_CHASSIS.
- The sole intentional galvanic bond is at the common power-entry point on the Power Module, immediately before the eFuse.
- This location is downstream of the source-selection / OR-ing stage, so the bond point remains correct regardless of whether PoE, USB-C, or battery input is active.
Local board restriction.
- All non-Power-Module boards that implement GND_CHASSIS must keep that local chassis net isolated from signal/power GND.
- Local connector shields, EMI landing pads, and mounting features may join the chassis domain, but they must not create a second DC bond.

Rationale

Gives enclosure-connected boards the same grounding rule when viewed in isolation.
Preserves the legitimate exemption for internal hat/daughterboard modules.
Makes mounting-hole treatment consistent across all PCB designs.
Preserves the EMC intent of using the enclosure as the transient/shield return path.
Keeps the single-point bond at the best location for all input-source combinations.

Supersession / Obsolescence

DEC-023 remains valid as the concrete JDB instance of the daughterboard exemption.
Earlier wording in the Global Routing Spec that left the exemption implicit and under-specified is obsolete.

Impact

Update design/Standards/Global_Routing_Spec.md to make the enclosure-connected-board rule and daughterboard exemption explicit.
Add or revise grounding cross-references in every board-level Design_Spec.md so the single-bond rule is visible even when a board spec is read on its own.
Keep the Power Module documentation explicit that the single bond is located at the common power-entry point immediately before the eFuse.

Cross-ref

DEC-020, DEC-023, DEC-038, design/Standards/Global_Routing_Spec.md §4–§5, design/Standards/Certification_Evidence.md §2.2.

Open Questions

Questions raised during design review that are deferred pending further investigation or a future decision.

QUE-001 — Exposed ENIG on Rib Clearway for GND_CHASSIS EMI Bonding

Status: Closed — resolved by DEC-020 (2026-04-08)
Raised: 2026-04-04
Area: Power Module / All Boards — PCB Finish & EMC

Background

The Power Module enclosure uses internal aluminium compression ribs that locate the PCB within the "Power Can". The supercap block §4 defines a 2.0mm rib clearway (14mm pitch, 12mm cell body) as a no-fly zone for traces on all layers. A separate GND_CHASSIS copper pour already exists in the supercap shadow zone beneath the cells (§5).

The question is whether the rib clearway should have an explicit solder mask opening (exposed ENIG) on the top copper layer, connected to the GND_CHASSIS net, so that when the PCB seats in the enclosure the aluminium ribs make direct electrical contact with the board's chassis ground. This is a standard EMC bonding technique used in Eurocard/VME card-cage designs.

What the change would involve

If accepted, the following updates would be made:

Power Module Design_Spec.md §4 — Add bullet:
- Rib Clearway ENIG Bond: A solder mask opening (exposed ENIG) is placed in the 2.0mm rib clearway gap on the top copper layer, connected to GND_CHASSIS. Contact with the aluminium enclosure rib creates a distributed chassis ground bond at the supercap block location.
Power Module Board_Layout.md — Add keepout note:

Rib clearway gap: solder mask open, GND_CHASSIS copper strip, min 1.5mm wide × full rib depth.
All other boards (Controller, Stator, Encoder) — Assess whether their enclosure ribs also warrant the same treatment and add matching callouts if so.
DEC-020 — Create a decision entry recording the EMC rationale, referencing the single-point GND_CHASSIS bond rule in Certification_Evidence.md §2.2.

Considerations

Factor	Note
Contact reliability	ENIG is ideal — hard, oxidation-resistant, consistent contact resistance
Enclosure material	Aluminium — no galvanic corrosion risk with ENIG
GND_CHASSIS topology	Single-point bond already defined (Cert_Evidence §2.2); rib contact adds distributed HF bond — compatible if star-point rule maintained for DC
Mechanical tolerance	Rib must be tight-fitting or spring-loaded to ensure reliable electrical contact
Other boards	Only applies where enclosure ribs contact the PCB — needs mechanical review per board

Resolution

Accepted. See DEC-020. Decision: expose ENIG on rib clearway zones, add minimum 2-mil polyimide (Kapton) tape on supercap bodies, and add conductive elastomer gasket strip at the rib-to-PCB contact interface. Other boards deferred pending mechanical design documentation (rib presence unconfirmed for Stator/Encoder/Rotor; Controller noted as using 3D-printed prototype chassis with future metal chassis EMI gaskets per Mechanical_Design.md §3).

QUE-002 — Prototype Bench-Testing Cable Strategy for Rotor Stack Connectors

Status: CLOSED — 2026-04-08
Raised: 2026-04-05
Area: All Boards — Rotor Interface Connectors (ERF8/ERM8 0.8mm pitch) & Extension/Reflector Links

Resolution

Break-off PCB coupons are to be included on the Rotor, Stator, Extension, and Reflector boards. Each coupon is a small PCB tab attached to the main board by mousebite perforations. One coupon per ERx8 connector. Each coupon fans out the 0.8mm pitch Samtec ERx8 pads to a standard 2.54mm pitch shrouded IDC box header, allowing standard ribbon cable assemblies to be used for initial bench testing without full stack assembly.

Coupon types required:

ERx8 Connector	Pins	IDC Header
ERM8-005 / ERF8-005	10 (2×5)	2×5 IDC box header, 2.54mm pitch
ERM8-010 / ERF8-010	20 (2×10)	2×10 IDC box header, 2.54mm pitch
ERM8-020 / ERF8-020	40 (2×20)	2×20 IDC box header, 2.54mm pitch

Per-board coupon provision:

Rotor: 6 coupons — J1 (ERM8-005), J2 (ERM8-005), J3 (ERM8-010), J4 (ERF8-005), J5 (ERF8-005), J6 (ERF8-010)
Stator: 4 coupons — J8 (ERM8-020) + J1/J2/J3 for Slot 1 test (ERF8-005 ×2, ERF8-010 ×1)
Extension: 6 coupons — J1 (ERM8-005), J2 (ERM8-005), J3 (ERM8-010), J4 (ERF8-005), J5 (ERF8-005), J6 (ERF8-010)
Reflector: 3 coupons — J1 (ERM8-005), J2 (ERM8-005), J3 (ERM8-010)

For final assembly the coupons are snapped off at the mousebite perforations and the ERx8 connectors mate directly board-to-board. Coupon IDC connector selection (shrouded box header part numbers) and exact PCB fanout geometry to be defined at schematic/layout phase.

Background

The rotor-to-rotor, rotor-to-Stator, and rotor-to-Reflector/Extension connections all use the Samtec Edge-Rate ERF8/ERM8 0.8mm pitch family, which are direct board-to-board connectors with no off-the-shelf cable assembly equivalent at standard distributors. During prototype bench testing it will not always be practical to have all boards physically stacked.

The Extension/Reflector link (J7 on Stator, J7/J8 on Extension, J4 on Reflector) and the Encoder ports (Stator J4-J6) use 2.54mm pitch shrouded IDC headers for which standard ribbon cable assemblies are readily available.

Questions to Resolve Before Prototype Build

ERF8/ERM8 0.8mm pitch: Are Samtec ERCD/ERCC cable assemblies available and stocked at DigiKey or Mouser for the ERF8-005 and ERF8-010 series? If not, what is the preferred bench-testing strategy (e.g., small bridge PCBs, short rigid extender boards, or FPC/FFC with pitch adapter)?
Connector selection review: Confirm that ERF8/ERM8 is still the correct family for the final design before committing to prototype PCB orders — alternative connector families may offer cable-assembly options without changing the electrical design.
2.54mm IDC cables: Confirm standard IDC ribbon cable lengths and sources for Stator J7 (16-pin 2×8) and Stator J4-J6 encoder ports (26-pin 2×13).

Note

This question was deferred to prioritise getting the connector definitions consolidated. The connector designators and signal assignments are considered stable (pending QUE-002 resolution). If a connector family change is required for prototype cabling, the affected documents are: Stator/Design_Spec.md, Extension/Design_Spec.md, Reflector/Design_Spec.md, Rotor/Design_Spec.md, Consolidated_BOM.md, and the Design_Log connector inventory.

INC Review History

This section records all INC (inconsistency) items tracked during the design process. Each item was identified during design review, verified, and resolved. All items are closed.

INC	Area	Description	Original Value	Corrected Value	Status
INC-01	Power Module eFuse	UVLO/OVLO thresholds inconsistent between README and Design_Spec	README: 12V UVLO / 16V OVP	11.0V UVLO / 16.9V OVLO (per Design_Spec §5)	✅ Resolved — README corrected
INC-02	Power Module eFuse	eFuse current limit insufficient for 75W USB-C path. TPS259474L max 5.5A with no headroom at 5.0A worst case	TPS259474L (5.5A ILIM)	TPS25980 (7A ILIM, 16.9V OVLO, VQFN-24). See DEC-005	✅ Resolved — DEC-005
INC-03	Power Module 5V Buck	Single buck insufficient for CM5 25W + other loads	LM61460-Q1 (6A)	Dual LMQ61460-Q1 interleaved (12A total). See DEC-007	✅ Resolved — DEC-007
INC-04	Power Module PD Emulator	TPS25750 PDO listed as "5V/6A" — not a valid USB-C PD current at 5V	"5V/6A" (invalid)	5V/5A (25W maximum at 5V per USB-C PD spec). See DEC-008	✅ Resolved — DEC-008
INC-05	Link-Alpha BtB Connector	3V3_SYSTEM routed from CM5 to Power Module on pins 21–24 for RJ45 LED anodes — cross-domain dependency	3V3_SYSTEM on pins 21–24 (input from CM5)	Removed. 3V3_ENIG generated locally on Power Module. Pins 21–22 → 5V_MAIN; pins 23–24 → GND. See DEC-001	✅ Resolved — DEC-001
INC-06	Power Module PoE	Ag5300 PoE module only supports 802.3at (25.5W PD) — insufficient for full system load ~42W	Ag5300 (802.3at, 25.5W)	Discrete: TPS2372-4 + TPS23730 + Coilcraft POE600F-12LD (802.3bt Type 4 / Class 8, 72W system; T2 transformer = 60W). See DEC-002	✅ Resolved — DEC-002
INC-07	Power Module / Controller	"3.3V/5A Rotors Buck" placed on Controller Board in README; contradicts central power generation principle	README: Rotor Buck on Controller Board	All rails on Power Module. Rotor stack uses 3V3_ENIG. See DEC-011	✅ Resolved — DEC-011
INC-08	Power Module I2C	I2C pull-ups (SDA/SCL 4.7kΩ) tied to 3V3_SYSTEM — invalid once 3V3_SYSTEM removed from Power Module	Pull-ups to 3V3_SYSTEM	Pull-ups moved to 3V3_ENIG	✅ Resolved
INC-09	Power Module Design_Spec	Internal conflict: §1 stated "16.5V OVP"; §5 stated "17V OVLO" — two different values in same document	§1: 16.5V OVP	16.9V OVLO (consistent with TPS25980 fixed OVLO variant; §1 corrected)	✅ Resolved — auto-resolved (16.5V reference not found in any current file)
INC-10	Power Module BOM	Reference designator collision: R1–R3 used for both eFuse ladder resistors AND I2C/reset pull-ups in the same document	R1–R3 dual-use	eFuse ladder: R1/R2/R3. I2C pull-ups: R7/R8. Reset pull-up: R9	✅ Resolved — designators renamed
INC-11	Power Module Battery	BATT_PRES_N pull-up R6 tied to 3V3_SYSTEM — invalid once 3V3_SYSTEM removed	R6 pull-up to 3V3_SYSTEM	R6 pull-up moved to 3V3_ENIG	✅ Resolved
INC-12	Link-Alpha BtB Connector	Power cluster labelled "6A Delivery Cluster" — outdated after dual 12A buck upgrade and pin reallocation	"6A Delivery Cluster" (16 pins)	9A delivery (18 pins × 0.5A/pin after reallocation). Label updated	✅ Resolved
INC-13	Power Module USB-C	STUSB4500 specified to negotiate 15V/3A (45W) — only 56.7% eFuse utilisation violation at worst-case 42.5W load	STUSB4500: 15V/3A (45W)	STUSB4500: 15V/5A (75W). See DEC-006	✅ Resolved — DEC-006
INC-14	Controller Diagnostic Banks	Diagnostic Bank-Alpha and Bank-Beta have no ESD protection; exposed ENIG pads treated as external interfaces	No ESD on diagnostic banks	Deferred to post-prototype. Accept risk for prototype stage. See DEC-010	✅ Resolved — DEC-010 (deferred)
INC-15	Controller/Power Module	Internal conflict in Board_Layout.md: bullet list said I2C=pins 35–40, 3V3_ENIG=pins 41–44; ASCII diagram said I2C=35–38, 3V3_ENIG=39–44	Bullets: I2C 35–40; 3V3_ENIG 41–44	ASCII diagram authoritative: I2C 35–38, 3V3_ENIG 39–44 (6 pins at 51.4% utilisation)	✅ Resolved — ASCII diagram is authoritative
INC-16	Board_Layout.md ETH LED diagram	ETH LED diagram showed PIN 27 = ETH_LED_ACT; main pin map shows pins 27–30 = GND Isolation Moat	Diagram: PIN 27 = ETH_LED_ACT	Correct: PIN 26 = ETH_LED_ACT; PIN 27 = GND Moat	✅ Resolved
INC-17	Power Module Battery	eFuse OVLO margin: with 16.9V OVLO and 4.2V/cell BMS (16.8V max), only 0.1V margin — risk of nuisance trips	BMS max 4.2V/cell (16.8V); OVLO 16.9V; margin 0.1V	BMS must use 4.1V/cell max (16.4V total for 4S), giving 0.5V margin. Added to Design_Spec §2. See DEC-005	✅ Resolved
INC-18	Power Module Design_Spec	Battery BMS charge voltage not specified in design spec — required to protect against OVLO nuisance trips	No BMS charge spec	Added: "BMS max charge voltage = 4.1V/cell (16.4V for 4S)" to Power Module §2 Battery Interface	✅ Resolved
INC-19	Power Module PoE	Ag5300/Ag53000 is 802.3at only (25.5W PD). No 802.3bt Type 4 PCB module found. Architecture change required: Type 3 (51W) insufficient; Type 4 (72W) required	Ag5300/Ag53000 (802.3at SIL module)	Discrete two-stage: TPS2372-4 (PD) + TPS23730 + POE600F-12LD (ACF transformer). See DEC-002	✅ Resolved — DEC-002
INC-20	Power Module Supercap	Supercap charge path had no current limiting — would cause excessive inrush and violate 75% utilisation rule under PoE	Supercap directly on 5V_MAIN bus	LTC3350 soft-charge via RICHARGE resistor; 0.5A limit under PoE. See DEC-004	✅ Resolved — DEC-004
INC-21	Power Module J2	Component selection locked: RJ45 MagJack	—	Würth 7499111121A (SMT, shielded, 2-LED, 10/100/1000)	✅ Locked
INC-22	Power Module ESD	Component selection locked: Ethernet ESD arrays	—	2× TI TPD4E05U06QDQARQ1 (0.8pF, ±15kV, −40°C to +125°C, U-DFN-10). DigiKey: 296-40696-1-ND; Mouser: 595-PD4E05U06QDQARQ1; JLCPCB: C81353	✅ Locked
INC-23	Power Module Bob Smith	Component selection locked: Bob Smith termination network	—	4× 75Ω 0402 ±1% resistors + 1× 10nF Y1-class capacitor to GND_CHASSIS	✅ Locked
INC-24	All Boards	Encoder detailed design review phase complete. Two consecutive clean passes (R56 + R57) achieved across all 24 design documents. Key corrections during cycle: GPIO 20/24 swap propagated to all files (R50/R55); LDO load 2.20A→2.11A propagated to all files (R50–R53); Power_Budgets.md CSS2H build qty corrected to 3; JTAG topology (BtB vs ribbon) documented in JTAG_Integrity.md, Extension Design_Spec, Reflector Design_Spec. Extension U1 buffer (SN74LVC2G125DCUR) confirmed correct and intentional.	—	—	✅ Phase complete

Board Connector Inventory

The following table lists all physical connectors across every board in the Enigma-NG system. This list should be manually verified against the original intended design to confirm no specification changes have inadvertently altered connector placement, orientation, or mating requirements.

Power Module

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	Notes
J1	Link-Alpha BtB — 80-pin socket to Controller Board	Samtec ERM8-040-05.0-S-DV-K-TR	ERM8-040	200-ERM8040050SDVKTR	SAM8613CT-ND	Male header (ERM8). Mating female on Controller (ERF8). Gold-plated, 0.5A/pin
J2	RJ45 MagJack with integrated magnetics	Würth 7499111121A	7499111121A	710-7499111121A	1297-1070-5-ND	SMT, shielded, 2 integrated LEDs (green/yellow), 10/100/1000 PoE compatible
J3	Battery connector — 5-pin Micro-Fit 3.0 THT vertical	Molex 43650-0519	43650-0519	538-43650-0519	WM14587-ND	5-circuit, 1-row, gold contacts, board lock, 3mm pitch. ⚠️ MPN corrected (43045-0512 does not exist)

Controller Board

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	Notes
J1	Link-Alpha BtB — 80-pin socket to Power Module	Samtec ERF8-040-05.0-S-DV-K-TR	ERF8-040	200-ERF8040050SDVKTR	SAM8621CT-ND	Female socket (ERF8). Mating male on Power Module (ERM8)
J2	Link-Beta BtB — 40-pin socket to Stator Board	Samtec ERF8-020-05.0-S-DV-K-TR	ERF8-020	200-ERF8020050SDVKTR	SAM8619CT-ND	Female socket (ERF8). Mating male on Stator (ERM8-020). 40-pin per DEC-015
J3	USB 3.0 — Dual-stacked Type-A port	Molex 48406-0003	48406-0003	538-0484060003	WM1394-ND	Dual-stack Type-A, 5.0mm protrusion through chassis
J4	HDMI — Full-size Type-A	TE Connectivity 2007435-1	2007435-1	571-2007435-1	A125057-ND	Full-size HDMI Type-A, 5.0mm protrusion through chassis
—	Diagnostic Bank-Alpha	2×10 ENIG Gold looped probe pads	—	—	—	2.54mm pitch, placed behind BtB header. Not a separate connector; probed directly with logic analyser clips
—	Diagnostic Bank-Beta	2×10 ENIG Gold looped probe pads	—	—	—	2.54mm pitch, L1 layer. Monitors LINK-BETA grouped power rails, I²C extension, and JTAG return path after DEC-037 — see Controller/Board_Layout.md Diagnostic Bank-Beta.
—	JTAG Daughterboard link (to FT232H board)	1×5 INPUT header + 1×10 JTAG header	—	—	—	2.54mm ENIG male headers on Controller. JDB female headers mate here. USB 2.0 to CM5 internally

Stator Board

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	Notes
J1-J3	Rotor 1 interface sockets (1 slot × 3 connectors: JTAG ERF8-005, Power ERF8-005, ENC ERF8-010) — cross-ref Rotor/Design_Spec.md §3.4	ERF8-005 (J1+J2) / ERF8-010 (J3)	200-ERF8005050SDVKTR (J1+J2) / 200-ERF8010050SDVKTR (J3)	SAM13517CT-ND (J1+J2 CT) / SAM8618CT-ND (J3 CT)	C7273978 (J1+J2) / C3646170 (J3)	ERF8 0.8mm pitch female sockets. Rotor 1 input side only (serial chain — not 30 slots). J1 pin 6 = TTD (outgoing TDI).
J4-J6	Encoder Port headers (×3: HID J4, Plugboard A J5, Plugboard B J6) — 26-pin 2×13 shrouded box header	Amphenol T821126A1S100CEU (2×13, 2.54mm)	T821126A1S100CEU	— (RS-Online 832-3503)	—	THT, shrouded, keyed. Pinout definition owner — see Stator/Board_Layout.md J4–J6. JLCPCB C3013501
J7	Extension/Reflector Link — 16-pin shrouded box header	Adam Tech BHR-16-VUA (2×8, 2.54mm)	BHR-16-VUA	737-BHR-16-VUA	2057-BHR-16-VUA-ND	THT, shrouded. Power, ENC_DATA, TTD_RETURN (pin 15). Pinout definition owner — see Stator/Board_Layout.md J7. JLCPCB C17692295
J8	Link-Beta BtB — 40-pin plug to Controller Board	Samtec ERM8-020-05.0-S-DV-K-TR	ERM8-020	200-ERM8020050SDVKTR	SAM8611CT-ND	Male plug (ERM8). Mating female on Controller (ERF8-020). 40-pin per DEC-015
—	JTAG Aux header	2×5 2.54mm shrouded	—	—	—	Pin pattern: GND\|TCK\|GND\|TMS\|GND\|TDI\|GND\|SYS_RESET_N\|GND

Rotor Board (×30)

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	JLCPCB Part #	Notes
J1	JTAG input — ERM8 male header (input side; plugs into Stator J1 ERF8 or Extension J4 ERF8)	Samtec ERM8-005-05.0-S-DV-K-TR (10-pin, 0.8mm pitch)	ERM8-005	200-ERM8005050SDVKTR	612-ERM8-005-05.0-S-DV-K-TRCT-ND	C3649741	Male (ERM8). Input side. Authority: Rotor/Design_Spec.md §3.4
J2	Power input — ERM8 male header (3V3_ENIG ×5, GND ×5)	Samtec ERM8-005-05.0-S-DV-K-TR (10-pin, 0.8mm pitch)	ERM8-005	200-ERM8005050SDVKTR	612-ERM8-005-05.0-S-DV-K-TRCT-ND	C3649741	Male (ERM8). Input power side
J3	ENC Data input — ERM8 male header (ENC_IN/ENC_OUT + GND)	Samtec ERM8-010-05.0-S-DV-K-TR (20-pin, 0.8mm pitch)	ERM8-010	200-ERM8010050SDVKTR	SAM8610CT-ND	C374877	Male (ERM8). Input ENC data
J4	JTAG output — ERF8 female socket (output side; receives next Rotor J1, Reflector J1, or Extension J1 ERM8 male)	Samtec ERF8-005-05.0-S-DV-K-TR (10-pin, 0.8mm pitch)	ERF8-005	200-ERF8005050SDVKTR	SAM13517CT-ND	C7273978	Female (ERF8). Output side. R1 (75Ω) in TTD output path
J5	Power output — ERF8 female socket (3V3_ENIG ×5, GND ×5)	Samtec ERF8-005-05.0-S-DV-K-TR (10-pin, 0.8mm pitch)	ERF8-005	200-ERF8005050SDVKTR	SAM13517CT-ND	C7273978	Female (ERF8). Output power side
J6	ENC Data output — ERF8 female socket (ENC_IN/ENC_OUT + GND)	Samtec ERF8-010-05.0-S-DV-K-TR (20-pin, 0.8mm pitch)	ERF8-010	200-ERF8010050SDVKTR	SAM8618CT-ND	C3646170	Female (ERF8). Output ENC data

Encoder Board

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	Notes
J1 (×64)	Plugboard cipher jack sockets (one per key/lamp position)	6.35mm (¼″) mono switched panel-mount jack socket — already purchased (eBay: SaiBuy.Ltd item 334364197440)	—	—	—	THT panel-mount. 64× per board (26 input + 26 output + 10 plugboard positions + 2 spare). Purchased.
J2	Data link to Stator — 26-pin 2×13 shrouded box header	Amphenol T821126A1S100CEU (2×13, 2.54mm)	T821126A1S100CEU	— (RS-Online 832-3503)	—	Mating connector for Stator J4/J5/J6. Cross-ref: Stator/Board_Layout.md J4–J6. JLCPCB C3013501
J3	Diagnostic looped probe pads	2×8 ENIG Gold pads	—	—	—	2.54mm pitch. Not a separate connector; probed directly

Reflector Board

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	JLCPCB Part #	Notes
J1	Rotor 30 output — JTAG (ERM8-005, 10-pin male, 0.8mm pitch)	Samtec ERM8-005-05.0-S-DV-K-TR	ERM8-005-05.0-S-DV-K-TR	200-ERM8005050SDVKTR	612-ERM8-005-05.0-S-DV-K-TRCT-ND	C3649741	Plugs into Rotor 30 J4 (ERF8-005 female). Definition owner: Rotor/Design_Spec.md §3.4
J2	Rotor 30 output — Power (ERM8-005, 10-pin male, 0.8mm pitch)	Samtec ERM8-005-05.0-S-DV-K-TR	ERM8-005-05.0-S-DV-K-TR	200-ERM8005050SDVKTR	612-ERM8-005-05.0-S-DV-K-TRCT-ND	C3649741	Plugs into Rotor 30 J5 (ERF8-005 female). Definition owner: Rotor/Design_Spec.md §3.4
J3	Rotor 30 output — ENC Data (ERM8-010, 20-pin male, 0.8mm pitch)	Samtec ERM8-010-05.0-S-DV-K-TR	ERM8-010-05.0-S-DV-K-TR	200-ERM8010050SDVKTR	SAM8610CT-ND	C374877	Plugs into Rotor 30 J6 (ERF8-010 female). Definition owner: Rotor/Design_Spec.md §3.4
J4	Interconnect to Stator/Extension — 16-pin shrouded box header	Adam Tech BHR-16-VUA (2×8, 2.54mm)	BHR-16-VUA	737-BHR-16-VUA	2057-BHR-16-VUA-ND	JLCPCB C17692295	Mating connector for Stator J7 (or Extension J7/J8). Carries TTD_RETURN on pin 15.
J5	Diagnostic looped probe pads	2×8 ENIG Gold pads	—	—	—	N/A	2.54mm pitch. Not a separate connector; probed directly

Extension Board

Ref	Description	Part / Series	MPN	Mouser PN	DigiKey PN	JLCPCB Part #	Notes
J1	Rotor group input — JTAG (ERM8-005, 10-pin male, 0.8mm pitch)	Samtec ERM8-005-05.0-S-DV-K-TR	ERM8-005-05.0-S-DV-K-TR	200-ERM8005050SDVKTR	612-ERM8-005-05.0-S-DV-K-TRCT-ND	C3649741	Plugs into previous rotor group's last rotor J4 (ERF8-005 female). Cross-ref: Rotor/Design_Spec.md §3.4
J2	Rotor group input — Power (ERM8-005, 10-pin male, 0.8mm pitch)	Samtec ERM8-005-05.0-S-DV-K-TR	ERM8-005-05.0-S-DV-K-TR	200-ERM8005050SDVKTR	612-ERM8-005-05.0-S-DV-K-TRCT-ND	C3649741	Plugs into previous rotor group's last rotor J5 (ERF8-005 female).
J3	Rotor group input — ENC Data (ERM8-010, 20-pin male, 0.8mm pitch)	Samtec ERM8-010-05.0-S-DV-K-TR	ERM8-010-05.0-S-DV-K-TR	200-ERM8010050SDVKTR	SAM8610CT-ND	C374877	Plugs into previous rotor group's last rotor J6 (ERF8-010 female).
J4	Rotor group output — JTAG (ERF8-005, 10-pin female, 0.8mm pitch)	Samtec ERF8-005-05.0-S-DV-K-TR	ERF8-005-05.0-S-DV-K-TR	200-ERF8005050SDVKTR	SAM13517CT-ND	C7273978	Receives next rotor group's first rotor J1 (ERM8-005 male). Cross-ref: Rotor/Design_Spec.md §3.4
J5	Rotor group output — Power (ERF8-005, 10-pin female, 0.8mm pitch)	Samtec ERF8-005-05.0-S-DV-K-TR	ERF8-005-05.0-S-DV-K-TR	200-ERF8005050SDVKTR	SAM13517CT-ND	C7273978	Receives next rotor group's first rotor J2 (ERM8-005 male).
J6	Rotor group output — ENC Data (ERF8-010, 20-pin female, 0.8mm pitch)	Samtec ERF8-010-05.0-S-DV-K-TR	ERF8-010-05.0-S-DV-K-TR	200-ERF8010050SDVKTR	SAM8618CT-ND	C3646170	Receives next rotor group's first rotor J3 (ERM8-010 male).
J7	Extension Port IN — 16-pin 2×8 shrouded box header	Adam Tech BHR-16-VUA (2×8, 2.54mm)	BHR-16-VUA	737-BHR-16-VUA	2057-BHR-16-VUA-ND	JLCPCB C17692295	Mating connector for Stator J7 (or previous Extension J8). Cross-ref: Stator/Board_Layout.md J7
J8	Extension Port OUT — 16-pin 2×8 shrouded box header	Adam Tech BHR-16-VUA (2×8, 2.54mm)	BHR-16-VUA	737-BHR-16-VUA	2057-BHR-16-VUA-ND	JLCPCB C17692295	Feeds next Extension J7 or Reflector J4. Cross-ref: Stator/Board_Layout.md J7
J9	Diagnostic looped probe pads	2×8 ENIG Gold pads	—	—	—	—	2.54mm pitch. Not a separate connector

JTAG Daughterboard (FT232H)

Ref	Description	Part / Series	Notes
J1	INPUT header — 5V_USB, 3V3_ENIG, D+, D−, GND	1×5 2.54mm female IDC	Power in (5V_USB + 3V3_ENIG) + internal USB 2.0 to CM5 via hat-header
J2	JTAG OUTPUT header (10-pin interleaved GND)	1×10 2.54mm female IDC	TCK/GND/TDI/GND/TDO/GND/TMS/GND/VREF/GND

Note for manual review: Items marked ??? or ⚠️ verify require confirmation before the BOM is finalised for procurement. In particular: Encoder J1 plug/jack type has not been selected; Controller J1 (ERF8) DigiKey PN SAM8621CT-ND (confirmed); Power Module J3 (43650-0519) DigiKey WM14587-ND (confirmed).

Open Work Items

The following items have been identified as future tasks. They are not yet scheduled but must not be forgotten.

OWI-001 — Test Coupons per Board

Add test coupon footprints to each board design to simplify manufacturing test and functional verification. Each board must be specified independently, as the relevant test signals and accessible nets will differ per board.

OWI-002 — PAS Definitions per Board

Define Provisional Acceptance Specifications (PAS) for each board, covering:

Basic board testing — power-on checks, continuity, short detection.
Functional testing via coupons — using coupon connections to real external devices to verify board functionality end-to-end (e.g. JTAG chain continuity, signal integrity, CPLD programming verification).

Each board must be specified independently.

OWI-003 — VHDL Pseudo-Code and CPLD Configuration Plans

For each CPLD in the system, create:

A configuration plan describing the intended logical function, I/O assignments, and state machine behaviour.
Pseudo-code or annotated VHDL stubs ready for handoff to software development.
Notes on how the VHDL can be exercised during PAS testing (OWI-002) to verify functional correctness.

Boards with CPLDs requiring this work: Encoder (×2), Stator (×1), Rotor (×1 per rotor, ×30 total).