SVC - sjsoftware/centurion-cpu6 GitHub Wiki
SVC - Supervisor Call
| Byte 1 | Byte 2 |
|-----------|-----------------|
| | | |
| 6 | 6 | 8 bit immediate |
Pseudocode
See also RSV
arg = *PC++
savex = X
X = PC
context (high) = CLR (there are some machine state bits in low nibble)
context (low) = CCR | ISR >> 4 (map bits are in high nibble of ISR)
*--S = context(low)
*--S = context(high)
*--S = savex(low)
*--S = savex(high)
*--S = arg
PC = 0100
MAP = 0
ISR &= 0xf (keep DMA map and set user map to zero)
Microcode
1b7 CRY1 r08 r08 RAM A+B P P P 633 33 (cc) JSR BADR READ.SWP (1b7) ; r08 *= 2 + 1 (r08 is 1 on entry)
CRY0 r00 r02 RAM D P P P 00f 0f (f0) BUS.WAIT INC.MAR READ.CONST (1b8) ; r02 <- f0
CRY1 r08 r00 PASS A+0 D D D 687 87 (78) LOAD.RIR READ.SWP (1b9) ; r08 += 1; RIR <- r08 (register 4 = X)
CRY0 r00 r00 PASS D D D D 6f9 f9 (06) LOAD.RR READ.ALO (687) ; RR <- ALO
I RLO CRY0 r02 r02 RAM D.XOR.A D D D 70a 0a (f5) READ.AHI (6f9) ; r02 <- AHI
I CRY0 r00 r01 RAM D D D D 6e2 e2 (1d) READ.RF (70a) ; r01 <- X (LO)
I RLO CRY0 r02 r02 RAMA D D D D 047 47 (b8) WRITE.RF LOAD.RR READ.RF (6e2) ; RF (LO) <- RR; RR <- r02; r02 <- X (LO)
I CRY0 r00 r00 RAM D P P P 466 66 (99) JSR PE WRITE.RF READ.DB (047) ; RF (HI) <- RR; r00 <- DB
CRY0 r00 r03 RAM D P P P 785 85 (7a) JSR DMA READ.MSR (048) ; r03 <- MSR (current level/H14 state bits)
CRY0 r06 r00 Q A D D D 671 71 (8e) READ.SWP (049) ; Q <- r06
CRY0 r04 r04 LSHQ A D D D 6b1 b1 (4e) READ.SWP (671) ; r04 <- r04/Q << 1
CRY0 r04 r04 LSHQ A D D D 6c2 c2 (3d) READ.SWP (6b1) ; r04 <- r04/Q << 1
CRY0 r04 r04 LSHQ A D D D 606 06 (f9) READ.SWP (6c2) ; r04 <- r04/Q << 1
CRY0 r04 r04 LSHQ NOT.D.AND.A P P P 007 07 (f8) READ.CONST (606) ; r04 <- (r04 & 7)/Q << 1 (r04 low nibble holds CL)
CRY0 r00 r05 RAM NOT.D D D D 6d7 d7 (28) READ.CCR (607) ; r05 <- CCR
CRY0 r05 r05 RAM NOT.D.AND.A P P P 0f0 f0 (0f) READ.CONST (6d7) ; r05 &= 0xf0 (mask out for CCR bits only)
CRY0 r04 r05 RAM A.OR.B P P P 785 85 (7a) JSR DMA READ.SWP (6d8) ; r04 |= r05
CRY0 r00 r09 RAM NOT.D P P P 00a 0a (f5) LOAD.RIR READ.CONST (6d9) ; r09 <- a; RIR <- a (S register)
I RLO CRY0 r00 r00 PASS A+Q D D D 6c4 c4 (3b) READ.SWP (6da) ; nop (RPL <- S (LO))
I CRY0 r00 r07 RAM D-1 D D D 6c6 c6 (39) LOAD.FLR LOAD.RR READ.RF (6c4) ; r07 <- S(LO) - 1; RR <- R07
CRY r00 r08 RAM D-1 D D D 6c8 c8 (37) LOAD.ALO LOAD.RR READ.RF (6c6) ; ALO <- RR; RR <- S(HI) - 1 - c
CRY0 r00 r00 PASS A.XOR.B D D D 677 77 (88) LOAD.AHI LOAD.RR READ.SWP (6c8) ; AHI <- RR; RR <- 0
CRY0 r00 r00 PASS A+Q P P P 102 02 (fd) LOAD.CCR READ.SWP (677) ; CCR <- 0 (clear condition codes)
CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA LOAD.AHI LOAD.ALO LOAD.MAR READ.SWP (678) ; swap ARs
CRY0 r00 r00 PASS A+Q D D D 617 17 (e8) READ.SWP (679) ; nop
CRY0 r05 r00 PASS A D D D PUSH 6bb bb (44) LOAD.DBR LOAD.RR READ.SWP (617) ; DBR <- r05; RR <- r05; BSR 6bb (push byte)
CRY0 r03 r00 PASS A D D D PUSH 6bb bb (44) INC.MAR LOAD.DBR LOAD.RR READ.SWP (618) ; MAR--; DBR <- r03; RR <- r03; BSR 6bb (push byte)
CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA INC.MAR READ.SWP (619) ; MAR--
CRY0 r01 r00 PASS A D D D PUSH 6bb bb (44) LOAD.DBR LOAD.RR READ.SWP (61a) ; DBR <- r01; RR <- r01; BSR 6bb (push byte)
CRY0 r02 r00 PASS A D D D PUSH 6bb bb (44) INC.MAR LOAD.DBR LOAD.RR READ.SWP (61b) ; MAR--; DBR <- r02; RR <- r02; BSR 6bb (push byte
CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA INC.MAR READ.SWP (61c) ; MAR--
CRY0 r00 r00 PASS A D D D PUSH 6bb bb (44) LOAD.DBR LOAD.RR READ.SWP (61d) ; DBR <- r00; RR <- r00; BSR 6bb (push byte)
CRY0 r09 r01 RAMA D P P P 000 00 (ff) LOAD.RIR READ.ALO (61e) ; RIR <- r09 (S); r01 <- ALO
CRY0 r01 r02 RAMA D P P P 000 00 (ff) LOAD.RR READ.AHI (61f) ; RR <- r01; r02 <- AHI
I RLO CRY0 r02 r00 PASS D.EQV.A P P P 0f0 f0 (0f) WRITE.RF LOAD.RR READ.CONST (620) ; RF <- RR; RR <- r00;
I CRY0 r00 r00 PASS NOT.D P P P 001 01 (fe) WRITE.RF LOAD.RR READ.CONST (621) ; RF <- RR; RR <- 01
CRY0 r00 r00 PASS NOT.D P P P 000 00 (ff) LOAD.AHI LOAD.RR READ.CONST (622) ; AHI <- RR; RR <- 00
CRY0 r06 r06 RAM D.AND.A P P P 0f0 f0 (0f) READ.CONST (623) ; r06 &= 0f (keep DMA map, clear user map)
CRY0 r00 r00 PASS ZERO D D D 616 16 (e9) LOAD.ALO LOAD.MAP READ.SWP (624) ; MAP <- 0
CRY0 r00 r07 PASS A+Q D D D 100 00 (ff) DIR+ LOAD.MAR READ.SWP (616) ; Forwards; MAR <- WAR