RSV - sjsoftware/centurion-cpu6 GitHub Wiki
RSV - Return from supervisor
| Byte 1 |
|-----------|
| | |
| 0 F |
Pseudocode
See also SVC
Note that S must be pointing to a page from the user process mapped into the OS space at MAP 0.
P = PC
S++ (skip SVC operand)
PC = X
X(high) = *S++
X(low) = *S++
level = *S++
map = *S++
MAP = map
ISR = (map << 4) & f0 | ISR & 0f (restore internal MAP, keeping DMA MAP)
CLR = level
Microcode
50f CRY0 r00 r09 RAM NOT.D D D D 2ae ae (51) LOAD.RIR READ.CONST (50f)
CRY0 r00 r00 PASS A+Q D D D PUSH 48e 8e (71) READ.SWP (2ae)
CRY0 r00 r09 RAM NOT.D P P P 00a 0a (f5) LOAD.RIR READ.CONST (2af)
I RLO CRY0 r00 r09 RAM NOT.D P P P 004 04 (fb) READ.CONST (2b0)
I CRY1 r00 r00 RAM D+0 D D D 2d0 d0 (2f) LOAD.FLR LOAD.RR READ.RF (2b1)
CRY r00 r01 RAM D+0 P P P 000 00 (ff) LOAD.ALO LOAD.RR READ.RF (2d0)
CRY0 r09 r00 PASS A D D D 25b 5b (a4) LOAD.AHI LOAD.RIR READ.SWP (2d1)
I CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT LOAD.AHI LOAD.ALO LOAD.MAR READ.SWP (25b)
I RLO CRY0 r00 r00 PASS D D D D 738 38 (c7) BUS.RD LOAD.RR READ.RF (25c)
CRY0 r00 r00 PASS D D D D 25d 5d (a2) LOAD.AHI LOAD.RR READ.RF (738)
CRY0 r09 r08 RAM A P P P 63b 3b (c4) JSR BADR LOAD.ALO READ.SWP (25d)
CRY0 r00 r00 PASS A+Q D D D 0a6 a6 (59) BUS.WAIT INC.MAR READ.SWP (25e)
CRY0 r00 r00 PASS D P P P 7ae ae (51) JSR PE BUS.RD LOAD.RR READ.DB (0a6)
I CRY0 r00 r00 PASS A+Q P P P 643 43 (bc) JSR BADR WRITE.RF READ.SWP (0a7)
CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT INC.MAR READ.SWP (0a8)
CRY0 r00 r00 PASS D P P P 1be be (41) JSR PE BUS.RD LOAD.RR READ.DB (0a9)
I RLO CRY1 r09 r09 RAM A+0 P P P 643 43 (bc) JSR BADR WRITE.RF READ.SWP (0aa)
CRY0 r00 r04 RAM NOT.D P P P 0f0 f0 (0f) BUS.WAIT INC.MAR READ.CONST (0ab)
CRY0 r00 r02 RAM D P P P 1be be (41) JSR PE BUS.RD READ.DB (0ac)
CRY0 r09 r09 RAM A+B P P P 643 43 (bc) JSR BADR LOAD.RIR READ.SWP (0ad)
CRY0 r00 r00 PASS A+Q P P P 785 85 (7a) JSR DMA BUS.WAIT READ.SWP (0ae)
CRY0 r00 r08 PASS A+B P P P 73e 3e (c1) JSR PE LOAD.FLR LOAD.RR READ.SWP (0af)
I RLO CRY r01 r00 PASS A+0 D D D 2bb bb (44) WRITE.RF LOAD.RR READ.SWP (0b0)
I CRY0 r00 r03 RAM D P P P 000 00 (ff) WRITE.RF LOAD.RR READ.DB (2bb)
CRY0 r03 r03 RAMA A+B P P P 000 00 (ff) LOAD.MAP READ.SWP (2bc)
CRY0 r03 r03 RAM A+B P P P 000 00 (ff) READ.SWP (2bd)
CRY0 r03 r03 LSH A+B P P P 000 00 (ff) READ.SWP (2be)
CRY0 r04 r03 RAM A.AND.B P P P 000 00 (ff) READ.SWP (2bf)
CRY0 r04 r06 RAM NOT.A.AND.B P P P 000 00 (ff) LOAD.MAR READ.SWP (2c0)
CRY0 r03 r06 RAM A.OR.B D D D 2ad ad (52) BUS.RD READ.SWP (2c1)
CRY0 r02 r00 PASS A D D D 101 01 (fe) LOAD.ILR READ.SWP (2ad)