Page Table (Map) instructions

The Page Table is called the "Map" in the Centurion CPU6 ISA. The Front panel displays the Map index (Page Table index). There are 8 entries, 0-3 are supervisor space and privileged instructions can be executed. 4-7 are user space and privileged instructions will force an abort.

The SVC instruction will jump to address 0100 at map index 0, which is the trampoline for system calls.

The current map index is stored in the AM2901 register 6, along with the map index for DMA.

There are five Page Table instructions in the CPU6 assembler.

Instruction format

| Byte 1       | Byte 2           | Byte 3 - n | Byte n+1 - m |
|--------------|------------------|------------|--------------|
|      |       | 7654 | 3 2 | 1 0 |     |      |      |       |
|   2      E   |   S     M     N  | Operand 1  | Operand 2    |

S = Instruction Selector (0-5 are legal)
M = Addressing Mode for operand 1 (0-3), data size = 1
N = Mode for operand 2 (0-2), data size unknown (depends on operand 1)

Addressing modes:

0 is direct, the address of the data is the operand
1 is indexed displacement (complicated)
2 is indexed, the address of the data is in a register in the high and/or low nibble
3 is literal or immediate, the data is stored in the bytes following the instruction.

Mode 1:

(May be incorrect)

Form of operand is EA = (r1 + r2 + disp), not sure how this was formatted for XASSM.
displacement is either 8 bits signed or 16 bits, if r1 is odd then 16 bits, otherwise 8 bits.
If r2 is 0 (A register) then EA = (r1 + disp).
r1 is evened out e.g., if r1 is 3 then register 2 (B register) is used.
r2 must be even.

| Byte n      | Byte n + 1                     | Byte n + 2                     |
|-------------|--------------------------------|--------------------------------|
| 7654 | 3210 |              |                 |               |                |
|  r1     r2  | 8 bit disp or 16 bit high byte | 16 bit low byte if 16 bit disp |

Mode 2:

EA = (R)

|    7 6 5 4   |   3 2 1 0    |
| Op1 Register   Op2 Register |

If both operands are mode 2, then only one byte is used, otherwise the nibble for the other operand register is ignored.

Odd registers are illegal

Selector	Opcode	Operand 1	Operand 2	Description
0	LDM	Low 3 bits: page table map. High 5 bits: count	Address	Load Map - write count page table entries with page table map from Operand 2 address
1	STM	Low 3 bits: page table map. High 5 bits: count	Address	Store Map - read count page table entries with page table map to Operand 2 address.
2	LSM	Low 3 bits: page table map. High 5 bits: Page table index	Address	Load Single Map - Write Page File 1 entry from Operand 2 address
3	SSM	Low 3 bits: page table map. High 5 bits: Page table index	Address	Store Single Map - Read 1 entry to Operand 2 address.
4	FLM	Low 3 bits: page table map. High 5 bits: Page table index	Address	Fill Map. Writes 32-index entries from Operand 2 address

Operand 1

| 76543       | 210 |
| Count - 1   | Map |