Paging - retrotruestory/M1DEV GitHub Wiki

Paging

When paging is enabled, all addresses go through the address translation mechanism. This involves generating a 22-bit physical address by selecting a 2K page based on a direct index of the top 5 bits of the logical address into the page table, and concatenating the lower 11 bits of the logical address. A process' 64-entry page table is split in to 32 code page entries, and 32 data page entries. In user mode, the base of the page table is located via the Page Table Base (PTB) register. When in supervisor mode, the base is hard-wired to 0x0000. There also exists a mechanism to override the supervisor mode page table base and use the current PTB instead, as well as explicit selections for code and data accesses. The latter features are used in supervisor mode to copy data between the user and supervisor address spaces.

Each page table entry is 16 bits wide. The low 11 bits are used to select the page, and the upper 3 bits are used as page attribute flags. Two bits are reserved for expansion of either the address space or page attribute flags. The flags are:

• P - Page present.
• W - Page writeable
• M - Is this RAM or a device? (This is how we do device memory mapping)

To simplify the circuitry, these bits will only be written is supervisor mode using the Write Page Table Entry (WPTE) instruction. To keep track of pages written to, all new pages will be entered into the table a non-writeable. On the first write, we'll trap and the OS can make the page dirty in the OS page table and then turn on the writeable bit and resume