Microcode Sequencer - retrotruestory/M1DEV GitHub Wiki

Microcode Sequencer

• Each microinstruction has an 8-bit "next" field, which tells which microinstruction follows.
• If (next==0x00), then the next microinstruction address is the 4-bit output of a 16-line priority encoder or'd with 0x100. The least priority value is the address of the fetch microinstruction. The other values represent traps and interrupts, and the encoder value will vector control off to the appropriate interrupt or trap handling microcode. The fetch line is tied active, and so will take effect if there are no traps or interrupts pending.
• if (next==0xff), then the next microinstruction address is the value of the IR (instruction register). In other words, the value of the 8-bit opcode is treated as a direct index into the microcode store.
• Otherwise, the next field is or'd with 0x100 and that value is the address of the next microinstruction.
• Which of the above three cases is used is determined by two control lines - MISC[INIT_INST] and a logical line which says whether next equals 0x00. INIT_INST is low active, and is asserted only during the fetch microinstruction.
• Next==0x00 normally happens at the end of each sequence of microinstructions which represents an M1 instruction. However, we also want to interrupt normal execution in the event of a trap, reset or interrupt. In the interrupt case, we want to recognize the interrupt only at M1 instruction boundaries. That will happen normally the next time next == 0x00. For traps and reset, though, we need to break the flow immediately - even in the middle of a microcode instruction sequence. In these cases, there is some glue logic which will assert the asynchronous clear line of the 8-bit register holding next and resetting it to 0x00. When that happens, we in effect normalize the exceptional instruction interrupt events as if they were regular instruction boundaries. The different microcode vectors for each trap or interrupt case can then handle the cleanup for any needed state rollback or fault state collection.
• Conditional microcode branches are handled using the same mechanism as the trap's next reset scheme. If a conditional microcode branch is indicated and the condition is not met, next is reset just as it would have been had there been a trap. Care was taken when writing the microcode to ensure that no traps were possible during a microinstruction which indicated a conditional branch, so there is no ambiguity.
• The conditional logic is handled by computing the various branch conditions based on the current values of the MSW condition bits. Keep in mind when looking at the logic is that when a condition is met and the machine instruction branch is taken, that we don't take the microinstruction branch. The branch microcode is structured so that if the branch is not to be taken, the microcode sequence aborts before it finished. If the branch is to be taken, the microcode continues to load the target address into PC and MAR.