Magic-1 Technical Architecture Specifications

CPU Core Technical Details

Register Architecture

Register	Width	Purpose	Accessibility
A	16-bit	Accumulator	User mode
B	16-bit	Secondary accumulator	User mode
C	16-bit	Counter register	User mode
X/Y	16-bit	Index registers	User mode
SP	16-bit	Stack pointer	User mode
PC	16-bit	Program counter	Privileged
MBR	16-bit	Memory buffer register	Internal
MAR	22-bit	Memory address register	Internal
FLAGS	16-bit	Status flags	Privileged access
TLB_HI	16-bit	TLB high word	Privileged access
TLB_LO	16-bit	TLB low word	Privileged access

Status Flags (FLAGS Register)

• Bit 0: Zero (Z) - Set when result is zero
• Bit 1: Negative (N) - Set when result is negative
• Bit 2: Carry (C) - Set on unsigned arithmetic carry
• Bit 3: Overflow (V) - Set on signed arithmetic overflow
• Bit 4: Interrupt Enable (IE) - Controls interrupt processing
• Bit 5: Supervisor Mode (SM) - Indicates privileged mode
• Bit 6: Trap (T) - For single-step debugging
• Bit 7: Paging Enable (PE) - Controls memory translation

Instruction Formats

1. Format 1: [8-bit opcode]

   • No operands (implicit)
   • Example: rts, nop, halt

2. Format 2: [8-bit opcode][8-bit immediate]

   • 8-bit immediate value
   • Example: addi #5, ldi #20

3. Format 3: [8-bit opcode][8-bit register/mode]

   • Register or addressing mode specification
   • Example: add r2, lda (r3)

4. Format 4: [8-bit opcode][8-bit register/mode][16-bit immediate]

   • Extended format with 16-bit immediate
   • Example: jmp $2000, lda $3000(r2)

Addressing Modes

Mode	Encoding	Description	Computation	Example
Immediate	0000xxxx	Constant value	operand = imm	ldi #5
Register	0001xxxx	Register direct	operand = reg[x]	add r2
Register Indirect	0010xxxx	Memory via register	operand = mem[reg[x]]	add (r2)
Auto-increment	0011xxxx	Post-increment	operand = mem[reg[x]]++	add (r2)+
Auto-decrement	0100xxxx	Pre-decrement	operand = mem[--reg[x]]	add -(r2)
Indexed	0101xxxx	Base+offset	operand = mem[reg[x]+imm]	add 20(r2)
PC-relative	0110xxxx	PC+offset	operand = mem[PC+imm]	add 20(pc)
Absolute	0111xxxx	Direct memory	operand = mem[imm]	add $2000

Memory Management Unit

TLB Structure

• Size: 16 entries
• Associativity: 4-way set associative
• Page Size: 2 KB (2048 bytes)
• Address Structure: 11-bit offset + 5-bit VPN

TLB Entry Format

• TLB_HI:

  • Bits 15-11: ASID (Address Space ID)
  • Bits 10-6: VPN (Virtual Page Number)
  • Bit 5: Global (G)
  • Bits 4-0: Reserved

• TLB_LO:

  • Bits 15-6: PFN (Physical Frame Number)
  • Bit 5: Valid (V)
  • Bit 4: Dirty (D)
  • Bit 3: Uncacheable (UC)
  • Bit 2: User mode accessible (U)
  • Bits 1-0: Reserved

Memory Map

Address Range	Size	Purpose
0x0000-0x1FFF	8 KB	System ROM
0x2000-0x3FFF	8 KB	System RAM
0x4000-0xDFFF	40 KB	User Program Space
0xE000-0xEFFF	4 KB	I/O Devices
0xF000-0xFFFF	4 KB	System Variables

I/O Mapped Devices

Address	Device	Function
0xE000	UART0_DATA	Serial port data register
0xE001	UART0_STATUS	Serial port status register
0xE002	UART0_CONTROL	Serial port control register
0xE010	IDE_DATA	IDE data register
0xE012	IDE_ERROR	IDE error register
0xE014	IDE_SECTOR_CNT	IDE sector count register
0xE016	IDE_SECTOR	IDE sector number register
0xE100	TIMER0_COUNT	Timer 0 counter register
0xE102	TIMER0_CONTROL	Timer 0 control register

ALU Specifications

ALU Operations

Operation	Function	Description
0000	A + B	Addition
0001	A - B	Subtraction
0010	A & B	Bitwise AND
0011	A | B	Bitwise OR
0100	A ^ B	Bitwise XOR
0101	~A	Bitwise NOT
0110	A << 1	Logical shift left
0111	A >> 1	Logical shift right
1000	A >>> 1	Arithmetic shift right
1001	A * B	Multiplication (lower word)
1010	(A * B) >> 16	Multiplication (upper word)
1011	A / B	Division
1100	A % B	Remainder

Hardware Implementation Details

• ALU Chips: 74F381, 74F382, 74F182 cascaded for 16-bit operations
• Clock Speed: 2 MHz effective instruction rate
• Microcode ROM: AM27C256 5 EPROMs (5 chips total)
• Control Unit: Implemented using TTL logic with microcode sequencing
• Physical Implementation: 200+ TTL ICs on multiple wire-wrapped boards

Bus Architecture

• L-bus: 16-bit primary operand path
• R-bus: 16-bit secondary operand path
• Z-bus: 16-bit ALU output path
• System Bus: 22-bit address, 16-bit data, multiplexed

Instruction Pipeline

• Stage 1: Instruction fetch (IF)
• Stage 2: Instruction decode (ID)
• Stage 3: Execute (EX)
• Stage 4: Memory access (MEM)
• Stage 5: Write back (WB)
• Pipeline Bubbles: Introduced during branches and memory hazards

Timing Specifications

• Clock Frequency: 4 MHz crystal, divided to 2 MHz
• Microinstruction cycle: 500ns
• Average instruction: 2-3 micro-cycles (1-1.5μs)
• Memory access: 250ns typical
• Maximum throughput: ~2 MIPS peak, ~0.7 MIPS sustained

This technical specification represents the core architectural elements of the Magic-1 homebrew CPU system at a detailed implementation level.