Based on the Magic-1 source code, here's the key information about the processor architecture:

Magic-1 Processor Architecture

1. Registers

Core Registers:
- MSW (Machine Status Word)
- C (General purpose)
- PC (Program Counter) 
- DP (Data Pointer)
- SP (Stack Pointer)
- A (General purpose)
- B (General purpose)
- MDR (Memory Data Register)
- PTB (Page Table Base)
- SSP (System Stack Pointer)
- TPC (Temporary PC)
- MAR (Memory Address Register)

2. Operating Modes

Mode Bits in MSW:
- Bit 7: Paging Enable
- Bit 3: User/Kernel Mode (0=user, 1=kernel)
- Bits 2-0: Interrupt Enable/Status

Operating Modes:
1. Kernel Mode (Privileged)
   - Full access to all instructions
   - Direct I/O access
   - Page table management

2. User Mode (Unprivileged)
   - Restricted instruction set
   - No direct I/O
   - Limited memory access

3. Instruction Set

ALU Operations:
- ADD/ADC (Add with/without carry)
- SUB/SBC (Subtract with/without carry)
- AND (Logical AND)
- OR (Logical OR)
- XOR (Logical XOR)

Memory Operations:
- LD.8/LD.16 (Load 8/16-bit)
- ST.8/ST.16 (Store 8/16-bit)
- PUSH/POP
- LDHI/LDLO (Load high/low byte)

Control Flow:
- BR (Branch)
- BR.NE (Branch if not equal)
- BR.EQ (Branch if equal)
- CALL/RET
- RETI (Return from interrupt)

System Operations:
- HALT
- CLI (Clear interrupts)
- STI (Set interrupts)
- WCPTE (Write code page table entry)
- WDPTE (Write data page table entry)

4. Memory Management

Page Table Structure:
- 2KB page size
- Separate code/data page tables
- Page table entry flags:
  PAGE_PRESENT     0x8000
  PAGE_WRITEABLE   0x4000
  PAGE_SRAM        0x2000
  PAGE_DEVICE      0x0000
  PAGE_WAIT        0x0000
  PAGE_NO_WAIT     0x1000

5. Interrupt System

Interrupt Vector Table:
0 - IRQ5 (RTC)
1 - IRQ4 (Unassigned)
2 - IRQ3 (UART0)
3 - IRQ2 (UART1) 
4 - IRQ1 (IDE)
5 - IRQ0 (Unassigned)
6 - DMA Request
7 - SYSCALL
8-15 - System exceptions

6. Addressing Modes

- Immediate
- Register Direct
- Register Indirect
- Base+Offset
- Pre/Post Increment/Decrement

This architecture implements:

• 16-bit data path
• Hardware memory management
• Privileged operations
• Vectored interrupts
• Both 8 and 16-bit operations

The instruction execution is microcode-based with a 56-bit wide microinstruction controlling all internal operations.