Based on the provided source files, here's the key information about the Magic-1 microcode specification:

Magic-1 Microcode Architecture

Microinstruction Format

// Microinstruction word structure (56 bits total)
typedef struct {
    unsigned next:8;        // Next microop address
    unsigned latch:4;       // Register latch control 
    unsigned lmar:1;        // Latch MAR
    unsigned lmdrlo:1;      // Latch MDR low byte
    unsigned lmdrhi:1;      // Latch MDR high byte
    unsigned emdrlo:1;      // Drive MDR low byte
    unsigned emdrhi:1;      // Drive MDR high byte
    unsigned priv:1;        // Privileged instruction
    unsigned lmode:1;       // Latch mode bit
    unsigned lpaging:1;     // Latch paging enable
    unsigned misc:4;        // Misc control signals
    unsigned e_l:4;         // Left bus enable
    unsigned e_r:2;         // Right bus enable
    unsigned immval:2;      // Immediate value
    unsigned aluop_size:1;  // ALU operation size
    unsigned aluop:2;       // ALU operation
    unsigned carry:1;       // Carry control
    unsigned l_size:1;      // Latch size
    unsigned br_sense:1;    // Branch sense
    unsigned user_ptb:1;    // User page table base
    unsigned code_ptb:1;    // Code/data selection
} mcode_rec_t;

Key Instruction Categories

1. ALU Operations

#define OP_IR13 0   // From instruction
#define OP_AND  1   // Logical AND
#define OP_SUB  2   // Subtract
#define OP_ADD  3   // Add

2. Memory Operations

// Memory access size
#define WORD    0   // 16-bit access
#define BYTE    1   // 8-bit access

// Memory control
#define READLO  LMDRLO(1)
#define READHI  LMDRHI(1)
#define WRITELO EMDRLO(1)
#define WRITEHI EMDRHI(1)

3. Branch Control

// Branch conditions
#define B_NORMAL    0  // Non-negated test
#define B_NEGATED   1  // Negated test

// Branch sense values:
// 0x0: equal
// 0x1: equal
// 0x2: less than  
// 0x3: less equal
// 0x4: less than unsigned
// 0x5: less equal unsigned
// 0x6: equal
// 0x7: not equal

4. Register Control

// Register selects
#define R_MSW   1   // Machine Status Word
#define R_C     2   // C register
#define R_PC    3   // Program Counter
#define R_DP    4   // Data Pointer
#define R_SP    5   // Stack Pointer
#define R_A     6   // A register
#define R_B     7   // B register
#define R_MDR   8   // Memory Data Register

Instruction Decoding

1. Initial decode uses opcode as direct index into microcode ROM
2. Microcode sequences handle complex operations
3. Support for privileged instructions
4. Memory addressing modes
5. Condition code handling

The microcode implements a two-bus architecture with:

• Left bus for general routing
• Right bus for ALU/Memory operations
• Register-to-register transfers
• Memory-to-register transfers
• I/O operations