Magic‐1 Computer Emulator Technical Summary - retrotruestory/M1DEV GitHub Wiki

Magic-1 Computer Emulator Technical Summary

After reviewing the provided materials about the Magic-1 computer architecture, I can now outline the key technical aspects that our emulator will need to implement.

1. CPU Architecture

  • Word Size: 16-bit, big-endian architecture
  • Address Space: 22-bit physical address space (effectively 23-bit with device space)
  • Paging: 2KB page size with 32 code pages and 32 data pages per process
  • Visible Registers:
    • A - Accumulator (8/16-bit addressable)
    • B - General load/store and ALU operand register
    • C - Special-purpose count register for block operations
    • MSW - Machine Status Word (flags: Carry, Zero, Sign, Overflow, Mode, Paging, EI)
    • DP - Global data pointer
    • SP - Stack pointer (16-bit operations)
    • SSP - Supervisor stack pointer
    • PC - Program Counter
    • PTB - Page Table Base pointer
  • Processor Modes: Supervisor (privileged) and User modes

2. Memory Organization

  • Physical Memory: Up to 4MB addressable
  • Memory Map (when paging off):
    • 0x0000-0x3FFF: ROM or RAM (selected by front panel)
    • 0x4000-0x7FFF: Always RAM
    • 0xFF80-0xFFFF: Device memory (16-byte blocks)
  • Device Memory Map:
    • 0xFFF0-0xFFFF: UART #0
    • 0xFFE0-0xFFEF: UART #1
    • 0xFFD0-0xFFDF: Real-time clock
    • 0xFFB0-0xFFBF: IDE interface
    • 0xFFA0-0xFFAF: Front panel switches

3. Instruction Set

  • Opcode Format: One-byte opcode + up to 3 bytes of immediate operands
  • Addressing Modes: Register indirect with offset, frame local with offset, global with offset, immediate, push, pop
  • Instruction Types: ALU operations, memory transfers, branches, system control, block operations

4. Microcode System

  • Format: 56-bit wide microinstructions across five 512x8-bit PROMs
  • Organization:
    • Bottom half (0x00-0xFF): Direct opcode mappings
    • Top half (0x100-0x1FF): Microcode sequences
  • Execution Cycle: Fetch/decode/execute spanning multiple clock cycles

5. I/O System

  • Serial: Dual UART interfaces
  • Storage: IDE/CF card interface
  • Timing: Real-time clock
  • User Interface: Front panel with hex display
  • Interrupt System: 6 interrupt channels (IRQ0-IRQ5)

6. Boot Process

  • Initial State: Supervisor mode, paging off, interrupts disabled
  • Boot Loading:
    • Load BIOS/bootloader from ROM
    • Initialize hardware devices
    • Load OS from CF card image
    • Set up page tables
    • Transfer control to OS

7. Emulator Requirements

Our emulator will need to implement:

  1. Core CPU Emulation:

    • Complete register set and ALU functionality
    • Accurate instruction timing
    • Full flag handling

  2. Memory Subsystem:

    • Paging system with hardware page table
    • Memory-mapped device handling
    • ROM/RAM switching

  3. Microcode Execution:

    • Loading 5 microcode files in BIN/HEX format
    • Microcode interpreter

  4. Peripheral Emulation:

    • UART interfaces with terminal I/O
    • CF card interface reading from image file
    • Real-time clock

  5. Debugger:

    • Memory/register inspection and modification
    • Breakpoints
    • Instruction tracing
    • Execution control (run/step/pause)

  6. GUI Interface:

    • Register display
    • Memory viewer
    • Execution controls
    • I/O device status panels

This emulator will provide an accurate recreation of the Magic-1 computer system, allowing it to run the original BIOS, bootloader, and operating system from CF card images.