void setup_address_space() {
    // 1. Set up initial page table mapping
    // 2. Enable paging
    // 3. Copy ROM to SRAM (0x20000-0x27FFF)
    // 4. Remap supervisor space
}

typedef struct {
    int pid;
    char name[16];
    char free;
    char loaded;
    char default_image;
    char split;
} t_process;

void read_intel_hex(unsigned int slot) {
    // 1. Parse Intel HEX records
    // 2. Validate checksums
    // 3. Write to appropriate memory space
    // 4. Handle split/unified spaces
}

void stage_boot_image(int slot) {
    // 1. Map transfer pages
    // 2. Copy image to physical memory
    // 3. Set up page tables
    // 4. Handle device page mapping
}

void read_sector(int sector, char *buf, int drive) {
    // 1. Check drive presence
    // 2. Handle CF vs IDE
    // 3. Calculate CHS if needed
    // 4. Perform transfer
}

#define UART0_BASE 0xFFF0  // Console
#define UART1_BASE 0xFFE0  // Auxiliary

typedef struct {
    uint8_t DATA;      // 0x0: Data I/O
    uint8_t IER;       // 0x1: Interrupt Enable
    union {
        uint8_t IIR;   // 0x2: Interrupt ID (Read)
        uint8_t FCR;   // 0x2: FIFO Control (Write)
    };
    uint8_t LCR;       // 0x3: Line Control
    uint8_t MCR;       // 0x4: Modem Control
    uint8_t LSR;       // 0x5: Line Status
    uint8_t MSR;       // 0x6: Modem Status
    uint8_t SCRATCH;   // 0x7: Scratch Register
} UART_Registers;

typedef struct {
    unsigned int present    : 1;    // 0x8000
    unsigned int writeable  : 1;    // 0x4000
    unsigned int sram      : 1;    // 0x2000
    unsigned int wait      : 1;    // 0x1000
    unsigned int address   : 12;   // Physical page number
} PageTableEntry;

typedef struct {
    char name[PNAME_SIZE];
    uint8_t split;         // Code/Data split flag
    uint16_t entry_point;
    uint32_t load_addr;
    uint32_t size;
    uint8_t loaded;
    uint8_t default_boot;
} BootImage;

#define NUM_IMAGES 8
typedef BootImage ImageTable[NUM_IMAGES];

void paging_control(void) {
    /* Page Table Structure:
     * - 64 entries per process
     * - 32 code pages (0x0000-0xFFFF)
     * - 32 data pages (0x0000-0xFFFF)
     * - Last page reserved for devices
     */
    
    // Sample page table initialization
    for(int i = 0; i < 64; i++) {
        if(i < 32) {
            // Code pages
            write_code_pte(i, PAGE_PRESENT | PAGE_SRAM | 
                          (physical_page << 12));
        } else {
            // Data pages
            write_data_pte(i - 32, PAGE_PRESENT | PAGE_WRITEABLE | 
                          PAGE_SRAM | (physical_page << 12));
        }
    }
}

void init_hardware(void) {
    // Post code for tracking boot progress
    to_post(0x01);
    
    // Configure UARTs
    init_uart(UART0_BASE, B38400);
    init_uart(UART1_BASE, B9600);
    
    // Reset and detect IDE/CF
    ide_reset();
    
    // Initialize RTC
    rtc_init();
    
    to_post(0x0A);  // Hardware init complete
}

typedef struct page_table_entry {
    uint16_t flags;
    uint32_t physical_addr;
} pte_t;

void write_page_table_entry(uint8_t pid, uint8_t page_num, pte_t *entry) {
    uint32_t pte_addr = (pid << 7) | (page_num & 0x3F);
    uint16_t *pt_base = (uint16_t *)0x10000;  // Page table base
    
    pt_base[pte_addr] = entry->flags | 
                        ((entry->physical_addr >> 11) & 0x0FFF);
}

void map_device_page(uint8_t pid) {
    pte_t device_pte = {
        .flags = PAGE_PRESENT | PAGE_DEVICE | PAGE_WAIT,
        .physical_addr = 0xFF000
    };
    write_page_table_entry(pid, 63, &device_pte);
}

#define IMAGE_HEADER_MAGIC 0x4D31  // "M1"

typedef struct {
    uint16_t magic;          // Magic number for validation
    uint16_t entry_point;    // Code entry point
    uint32_t code_size;      // Size of code segment
    uint32_t data_size;      // Size of data segment
    uint8_t  split;          // Split code/data flag
    uint8_t  reserved[7];    // Padding for alignment
    char     name[16];       // Image name
    uint16_t checksum;       // Header checksum
} boot_image_header_t;

#define IDE_BASE        0xFFB0
#define IDE_DATA        (IDE_BASE + 0)
#define IDE_ERROR      (IDE_BASE + 1)
#define IDE_SECCOUNT   (IDE_BASE + 2)
#define IDE_SECNUM     (IDE_BASE + 3)
#define IDE_CYLLOW     (IDE_BASE + 4)
#define IDE_CYLHIGH    (IDE_BASE + 5)
#define IDE_DRVHEAD    (IDE_BASE + 6)
#define IDE_STATUS     (IDE_BASE + 7)

int read_sector(uint32_t lba, uint8_t *buffer) {
    // Select drive and wait for ready
    outb(IDE_DRVHEAD, 0xE0 | ((lba >> 24) & 0x0F));
    while(!(inb(IDE_STATUS) & 0x40));  // Wait for DRDY
    
    // Set up LBA registers
    outb(IDE_SECCOUNT, 1);
    outb(IDE_SECNUM, lba & 0xFF);
    outb(IDE_CYLLOW, (lba >> 8) & 0xFF);
    outb(IDE_CYLHIGH, (lba >> 16) & 0xFF);
    
    // Issue READ command
    outb(IDE_STATUS, 0x20);
    
    // Wait for DRQ and transfer data
    while(!(inb(IDE_STATUS) & 0x08));
    for(int i = 0; i < 512; i++) {
        buffer[i] = inb(IDE_DATA);
    }
    
    return (inb(IDE_STATUS) & 0x01) ? -1 : 0;  // Check for error
}

typedef struct command {
    char key;                      // Single character command
    void (*handler)(void);         // Command handler function
    const char *description;       // Help text
    uint8_t requires_password;     // Security flag
} command_t;

static const command_t commands[] = {
    {'S', handle_set_drive,      "Set active drive", 0},
    {'P', handle_show_images,    "Show image table", 0},
    {'L', handle_load_image,     "Load boot image", 1},
    {'B', handle_boot_image,     "Boot an image", 0},
    {'D', handle_delete_image,   "Delete image", 1},
    {0, NULL, NULL, 0}  // Terminator
};

void command_loop(void) {
    char cmd;
    while(1) {
        print_prompt();
        cmd = get_char(CONSOLE);
        
        for(const command_t *cp = commands; cp->key; cp++) {
            if(toupper(cmd) == cp->key) {
                if(cp->requires_password && !verify_password()) {
                    printf("Access denied\n");
                    break;
                }
                cp->handler();
                break;
            }
        }
    }
}

typedef struct uart_interface {
    volatile uint8_t *base;
    uint16_t tx_head;
    uint16_t tx_tail;
    uint16_t rx_head;
    uint16_t rx_tail;
    uint8_t tx_buffer[256];
    uint8_t rx_buffer[256];
} uart_t;

static uart_t r_uart0 = { .base = (uint8_t*)UART0_BASE };
static uart_t r_uart1 = { .base = (uint8_t*)UART1_BASE };

int uart_putchar(uart_t *uart, char c) {
    while(!(uart->base[UART_LSR] & UART_XMIT_READY)) {
        // Wait for transmitter
    }
    uart->base[UART_DATA] = c;
    return 0;
}

int uart_getchar(uart_t *uart) {
    while(!(uart->base[UART_LSR] & UART_DATA_READY)) {
        // Wait for receiver
    }
    return uart->base[UART_DATA];
}

#define MAX_RECORD_SIZE 32

typedef struct {
    uint8_t  length;
    uint16_t address;
    uint8_t  type;
    uint8_t  data[MAX_RECORD_SIZE];
    uint8_t  checksum;
} hex_record_t;

int parse_hex_record(char *line, hex_record_t *record) {
    uint8_t computed_checksum = 0;
    
    if(line[0] != ':') return -1;
    
    // Parse record length
    record->length = hex_to_byte(line + 1);
    computed_checksum += record->length;
    
    // Parse address
    record->address = hex_to_word(line + 3);
    computed_checksum += (record->address >> 8) & 0xFF;
    computed_checksum += record->address & 0xFF;
    
    // Parse record type
    record->type = hex_to_byte(line + 7);
    computed_checksum += record->type;
    
    // Parse data bytes
    for(int i = 0; i < record->length; i++) {
        record->data[i] = hex_to_byte(line + 9 + (i * 2));
        computed_checksum += record->data[i];
    }
    
    // Verify checksum
    record->checksum = hex_to_byte(line + 9 + (record->length * 2));
    computed_checksum = (uint8_t)(-(int8_t)computed_checksum);
    
    return (computed_checksum == record->checksum) ? 0 : -1;
}

#define PASSWORD_HASH_SIZE 32
#define SALT_SIZE 16

typedef struct {
    uint8_t hash[PASSWORD_HASH_SIZE];
    uint8_t salt[SALT_SIZE];
} password_store_t;

static password_store_t stored_password;

bool verify_password(void) {
    char password[64];
    uint8_t computed_hash[PASSWORD_HASH_SIZE];
    
    printf("Enter password: ");
    get_string(password, sizeof(password), ECHO_PASSWORD);
    
    compute_hash(password, stored_password.salt, computed_hash);
    return (memcmp(computed_hash, stored_password.hash, 
            PASSWORD_HASH_SIZE) == 0);
}

typedef enum {
    ERR_NONE = 0,
    ERR_HARDWARE = -1,
    ERR_TIMEOUT = -2,
    ERR_CHECKSUM = -3,
    ERR_INVALID_IMAGE = -4,
    ERR_WRITE_PROTECTED = -5
} error_code_t;

typedef struct {
    error_code_t code;
    const char *message;
    uint8_t fatal;
} error_info_t;

static const error_info_t error_table[] = {
    {ERR_NONE, "Success", 0},
    {ERR_HARDWARE, "Hardware failure", 1},
    {ERR_TIMEOUT, "Operation timeout", 0},
    {ERR_CHECKSUM, "Checksum error", 0},
    {ERR_INVALID_IMAGE, "Invalid boot image", 0},
    {ERR_WRITE_PROTECTED, "Write protected", 0}
};

void handle_error(error_code_t code) {
    for(const error_info_t *ep = error_table; ep->message; ep++) {
        if(ep->code == code) {
            printf("Error: %s\n", ep->message);
            
            // Log error to diagnostic port
            diagnostic_log(ep->message, ep->code);
            
            if(ep->fatal) {
                printf("Fatal error - system halted\n");
                while(1) {
                    // System halt
                    asm volatile("halt");
                }
            }
            return;
        }
    }
}

#define WATCHDOG_BASE 0xFFC0
#define WATCHDOG_TIMEOUT 1000  // milliseconds

typedef struct {
    volatile uint16_t counter;
    volatile uint16_t control;
} watchdog_t;

static watchdog_t *const watchdog = (watchdog_t*)WATCHDOG_BASE;

void init_watchdog(void) {
    watchdog->control = 0x0001;  // Enable watchdog
    watchdog->counter = WATCHDOG_TIMEOUT;
}

void pet_watchdog(void) {
    watchdog->counter = WATCHDOG_TIMEOUT;
}

void watchdog_isr(void) {
    // Handle watchdog timeout
    handle_error(ERR_TIMEOUT);
}

#define MAX_LOG_ENTRIES 32

typedef struct {
    uint32_t timestamp;
    error_code_t code;
    char message[64];
} log_entry_t;

static struct {
    log_entry_t entries[MAX_LOG_ENTRIES];
    uint8_t head;
    uint8_t count;
} error_log;

void diagnostic_log(const char *message, error_code_t code) {
    log_entry_t *entry = &error_log.entries[error_log.head];
    
    entry->timestamp = get_rtc_time();
    entry->code = code;
    strncpy(entry->message, message, sizeof(entry->message) - 1);
    
    error_log.head = (error_log.head + 1) % MAX_LOG_ENTRIES;
    if(error_log.count < MAX_LOG_ENTRIES) {
        error_log.count++;
    }
}

#pragma pack(1)
typedef struct {
    uint16_t magic;           // Magic number 0x4D31 ("M1")
    uint16_t version;         // Format version
    uint32_t load_address;    // Load address for image
    uint32_t entry_point;     // Execution start address
    uint32_t code_size;       // Size of code segment
    uint32_t data_size;       // Size of data segment
    uint8_t  flags;          // Image flags
    char     name[16];       // Image name (null-terminated)
    uint32_t checksum;       // CRC32 of image
} BootImageHeader;
#pragma pack()

static bool validate_boot_image(const BootImageHeader* header) {
    if (header->magic != MAGIC_SIGNATURE) {
        log_error("Invalid magic number in boot image");
        return false;
    }

    uint32_t computed_crc = crc32(0, (uint8_t*)header + sizeof(header->checksum), 
                                 sizeof(BootImageHeader) - sizeof(header->checksum));
    
    if (computed_crc != header->checksum) {
        log_error("Boot image checksum mismatch");
        return false;
    }

    // Validate memory boundaries
    if (header->load_address + header->code_size + header->data_size > MAX_MEMORY) {
        log_error("Image exceeds memory boundaries");
        return false;
    }

    return true;
}

typedef struct {
    uint32_t start_addr;
    uint32_t size;
    bool is_code;
} MemoryRegion;

static bool allocate_image_memory(const BootImageHeader* header, 
                                MemoryRegion* code_region,
                                MemoryRegion* data_region) {
    // Allocate code segment
    code_region->start_addr = header->load_address;
    code_region->size = header->code_size;
    code_region->is_code = true;

    // Set up page tables for code region
    for (uint32_t addr = code_region->start_addr; 
         addr < code_region->start_addr + code_region->size;
         addr += PAGE_SIZE) {
        
        if (!map_page(addr, PAGE_PRESENT | PAGE_EXECUTE)) {
            return false;
        }
    }

    // Similar setup for data region
    data_region->start_addr = code_region->start_addr + code_region->size;
    data_region->size = header->data_size;
    data_region->is_code = false;

    return true;
}

typedef struct {
    uint32_t offset;
    uint32_t type;
    uint32_t addend;
} RelocationEntry;

static bool relocate_image(uint8_t* image_base, 
                         const RelocationEntry* relocations,
                         size_t reloc_count) {
    for (size_t i = 0; i < reloc_count; i++) {
        uint32_t* target = (uint32_t*)(image_base + relocations[i].offset);
        
        switch (relocations[i].type) {
            case RELOC_ABSOLUTE:
                *target = relocations[i].addend + (uint32_t)image_base;
                break;
            case RELOC_RELATIVE:
                *target = relocations[i].addend + 
                         (*target - (uint32_t)image_base);
                break;
            default:
                log_error("Unknown relocation type");
                return false;
        }
    }
    return true;
}

void execute_boot_image(const BootImageHeader* header) {
    typedef void (*entry_point_t)(void);
    entry_point_t entry = (entry_point_t)header->entry_point;

    // Disable interrupts
    asm volatile("cli");

    // Switch to image's page table
    switch_page_table(header->page_table);

    // Jump to entry point
    entry();

    // Should never return
    log_error("Boot image returned to loader");
    while(1) { }
}

struct MemoryTiming {
    uint8_t refresh_rate;
    uint8_t cas_latency;
    uint8_t ras_timing;
    uint8_t wait_states;
};

static void init_memory_controller(void) {
    volatile uint16_t* const MEM_CTRL = (uint16_t*)0xFF00;
    
    const struct MemoryTiming timing = {
        .refresh_rate = 15,  // 15ms refresh
        .cas_latency = 2,    // CAS Latency 2
        .ras_timing = 3,     // RAS timing
        .wait_states = 1     // 1 wait state
    };
    
    *MEM_CTRL = (timing.refresh_rate << 12) |
                (timing.cas_latency << 8) |
                (timing.ras_timing << 4) |
                timing.wait_states;
}

typedef struct {
    uint16_t base_addr;
    uint16_t baud_rate;
    uint8_t data_bits;
    uint8_t stop_bits;
    uint8_t parity;
} UartConfig;

static void configure_uart(const UartConfig* config) {
    // Set divisor latch
    uint16_t divisor = UART_CLOCK / (16 * config->baud_rate);
    outb(config->base_addr + LCR, 0x80);  // Enable DLAB
    outb(config->base_addr + DLL, divisor & 0xFF);
    outb(config->base_addr + DLH, (divisor >> 8) & 0xFF);
    
    // Configure line settings
    uint8_t lcr = ((config->data_bits - 5) & 0x3) |
                  ((config->stop_bits - 1) << 2) |
                  (config->parity << 3);
    outb(config->base_addr + LCR, lcr);
    
    // Enable FIFOs
    outb(config->base_addr + FCR, 0x07);
}

#define NUM_VECTORS 16

typedef struct {
    uint32_t vector_addr;
    void (*handler)(void);
    uint8_t priority;
} InterruptVector;

static void setup_interrupt_vectors(void) {
    static const InterruptVector vectors[] = {
        { 0x00, nmi_handler,      0 },
        { 0x04, uart0_handler,    2 },
        { 0x08, uart1_handler,    2 },
        { 0x0C, timer_handler,    1 },
        { 0x10, ide_handler,      3 },
        { 0x14, rtc_handler,      4 }
    };
    
    for (int i = 0; i < sizeof(vectors)/sizeof(vectors[0]); i++) {
        // Write vector address and handler
        *(uint32_t*)vectors[i].vector_addr = (uint32_t)vectors[i].handler;
        
        // Set interrupt priority
        set_interrupt_priority(i, vectors[i].priority);
    }
}

#define CLOCK_BASE 0xFF20
#define PLL_CTRL  (CLOCK_BASE + 0)
#define CLK_DIV   (CLOCK_BASE + 2)

struct ClockConfig {
    uint8_t pll_mult;     // PLL multiplier (2-16)
    uint8_t pll_div;      // PLL divider (1-8)
    uint8_t sys_div;      // System clock divider
    uint8_t periph_div;   // Peripheral clock divider
};

static void configure_system_clocks(const struct ClockConfig* config) {
    // Configure PLL
    uint16_t pll_ctrl = (config->pll_mult << 8) | config->pll_div;
    outw(PLL_CTRL, pll_ctrl);
    
    // Wait for PLL lock
    while (!(inw(PLL_CTRL) & 0x8000)) {
        continue;
    }
    
    // Set clock dividers
    uint16_t div_ctrl = (config->sys_div << 8) | config->periph_div;
    outw(CLK_DIV, div_ctrl);
}

#define IDE_BASE       0xFFB0
#define IDE_DATA       (IDE_BASE + 0)
#define IDE_ERROR      (IDE_BASE + 1)
#define IDE_FEATURES   (IDE_BASE + 1)
#define IDE_SECCOUNT   (IDE_BASE + 2)
#define IDE_SECTOR     (IDE_BASE + 3)
#define IDE_CYLLOW     (IDE_BASE + 4)
#define IDE_CYLHIGH    (IDE_BASE + 5)
#define IDE_DRVHEAD    (IDE_BASE + 6)
#define IDE_STATUS     (IDE_BASE + 7)
#define IDE_COMMAND    (IDE_BASE + 7)

typedef struct {
    uint8_t  present;       // Device presence flag
    uint8_t  is_cf;        // CompactFlash flag
    uint16_t cylinders;    // Number of cylinders
    uint8_t  heads;        // Number of heads
    uint8_t  sectors;      // Sectors per track
    uint32_t capacity;     // Total capacity in sectors
} ide_device_t;

static ide_device_t devices[2] = {0}; // Master and Slave

static int identify_device(uint8_t device) {
    uint16_t buffer[256];
    uint8_t status, cl, ch;
    
    // Select device
    outb(IDE_DRVHEAD, device ? 0xB0 : 0xA0);
    delay_ms(1);
    
    // Check for CompactFlash signature
    cl = inb(IDE_CYLLOW);
    ch = inb(IDE_CYLHIGH);
    
    if (cl == 0x14 && ch == 0xEB) {
        devices[device].is_cf = 1;
    }
    
    // Issue IDENTIFY command
    outb(IDE_COMMAND, 0xEC);
    status = inb(IDE_STATUS);
    
    if (status == 0) {
        return -1; // Device not present
    }
    
    // Wait for data ready
    while (((status = inb(IDE_STATUS)) & 0x80) != 0);
    
    // Read identification space
    for (int i = 0; i < 256; i++) {
        buffer[i] = inw(IDE_DATA);
    }
    
    // Parse identification data
    devices[device].present = 1;
    devices[device].cylinders = buffer[1];
    devices[device].heads = buffer[3];
    devices[device].sectors = buffer[6];
    devices[device].capacity = buffer[60] | (buffer[61] << 16);
    
    return 0;
}

#define SECTOR_SIZE 512

typedef enum {
    TRANSFER_READ,
    TRANSFER_WRITE
} transfer_mode_t;

static int transfer_sectors(uint8_t device, uint32_t lba, 
                          uint8_t count, void* buffer,
                          transfer_mode_t mode) {
    uint8_t cmd = (mode == TRANSFER_READ) ? 0x20 : 0x30;
    
    // Select device and write parameters
    outb(IDE_DRVHEAD, (device ? 0xF0 : 0xE0) | ((lba >> 24) & 0x0F));
    outb(IDE_SECCOUNT, count);
    outb(IDE_SECTOR, lba & 0xFF);
    outb(IDE_CYLLOW, (lba >> 8) & 0xFF);
    outb(IDE_CYLHIGH, (lba >> 16) & 0xFF);
    
    // Issue command
    outb(IDE_COMMAND, cmd);
    
    for (int i = 0; i < count; i++) {
        // Wait for DRQ
        while ((inb(IDE_STATUS) & 0x08) == 0) {
            if (inb(IDE_STATUS) & 0x01) {
                return -1; // Error
            }
        }
        
        // Transfer data
        if (mode == TRANSFER_READ) {
            for (int j = 0; j < SECTOR_SIZE/2; j++) {
                ((uint16_t*)buffer)[j] = inw(IDE_DATA);
            }
        } else {
            for (int j = 0; j < SECTOR_SIZE/2; j++) {
                outw(IDE_DATA, ((uint16_t*)buffer)[j]);
            }
        }
        
        buffer = (uint8_t*)buffer + SECTOR_SIZE;
    }
    
    return 0;
}

#define PAGE_SIZE           2048    // 2KB pages
#define PAGE_TABLE_ENTRIES  64      // 32 code + 32 data pages
#define PAGE_PRESENT       0x8000
#define PAGE_WRITEABLE    0x4000
#define PAGE_SRAM         0x2000
#define PAGE_WAIT         0x1000

typedef struct {
    uint16_t entries[PAGE_TABLE_ENTRIES];
} PageTable;

typedef struct {
    uint16_t ptb;          // Page Table Base
    PageTable *table;      // Pointer to page table
    uint8_t pid;          // Process ID (0-7)
} MMUContext;

static MMUContext current_context;

static uint32_t translate_address(uint16_t virtual_addr, bool is_code) {
    uint8_t page_index = (virtual_addr >> 11) & 0x1F;
    uint16_t offset = virtual_addr & 0x7FF;
    
    // Add 32 to page_index for data pages
    if (!is_code) {
        page_index += 32;
    }
    
    uint16_t pte = current_context.table->entries[page_index];
    
    if (!(pte & PAGE_PRESENT)) {
        handle_page_fault(virtual_addr);
        return 0xFFFFFFFF;
    }
    
    uint32_t physical_page = pte & 0x0FFF;
    return (physical_page << 11) | offset;
}

void mmu_switch_context(uint8_t pid) {
    current_context.pid = pid;
    current_context.ptb = pid << 7;  // PTB = PID * 128
    current_context.table = (PageTable*)(0x10000 + current_context.ptb);
    
    // Update hardware PTB register
    outw(MMU_PTB_REG, current_context.ptb);
}

int mmu_map_page(uint8_t page_num, uint32_t physical_addr, uint16_t flags) {
    if (page_num >= PAGE_TABLE_ENTRIES) {
        return -1;
    }
    
    uint16_t pte = (physical_addr >> 11) & 0x0FFF;
    pte |= flags & 0xF000;
    
    current_context.table->entries[page_num] = pte;
    return 0;
}

void handle_page_fault(uint16_t fault_addr) {
    uint8_t fault_page = (fault_addr >> 11) & 0x3F;
    bool is_code = fault_page < 32;
    
    // Log the fault
    printf("Page fault: addr=0x%04X page=%d %s\n",
           fault_addr, fault_page, is_code ? "code" : "data");
           
    if (is_code) {
        // Handle code page fault
        load_code_page(fault_page);
    } else {
        // Handle data page fault
        allocate_data_page(fault_page - 32);
    }
}

static void load_code_page(uint8_t page_num) {
    // Allocate physical page
    uint32_t phys_addr = allocate_physical_page();
    
    // Load page contents from boot image
    load_page_from_image(page_num, (void*)phys_addr);
    
    // Map the page
    mmu_map_page(page_num, phys_addr, 
                 PAGE_PRESENT | PAGE_SRAM);
}

#pragma pack(push, 1)
typedef struct {
    uint16_t magic;           /* 'M1' (0x4D31) */
    uint8_t  version;        /* Format version (current: 1) */
    uint8_t  flags;          /* Image flags */
    uint32_t load_address;   /* Base load address */
    uint32_t entry_point;    /* Execution entry point */
    uint32_t code_size;      /* Size of code segment */
    uint32_t data_size;      /* Size of data segment */
    uint32_t bss_size;       /* Size of BSS segment */
    char     name[16];       /* Image name (null-terminated) */
    uint32_t checksum;       /* CRC-32 of image content */
} BootImageHeader;
#pragma pack(pop)

#include "boot_image.h"
#include "mmu.h"
#include "crc32.h"

#define MAX_IMAGE_SIZE (512 * 1024)  /* 512KB maximum image size */

static uint8_t image_buffer[MAX_IMAGE_SIZE];

int load_boot_image(const char* image_name) {
    BootImageHeader* header = (BootImageHeader*)image_buffer;
    int status;
    
    /* Read image from storage */
    status = read_image_from_storage(image_name, image_buffer, MAX_IMAGE_SIZE);
    if (status < 0) {
        return status;
    }
    
    /* Validate header */
    if (header->magic != 0x4D31) {
        return -1;  /* Invalid magic number */
    }
    
    /* Verify checksum */
    uint32_t computed_crc = crc32(0, 
        image_buffer + sizeof(BootImageHeader), 
        header->code_size + header->data_size);
        
    if (computed_crc != header->checksum) {
        return -2;  /* Checksum mismatch */
    }
    
    /* Map memory regions */
    status = map_image_memory(header);
    if (status < 0) {
        return status;
    }
    
    /* Copy segments to memory */
    copy_segments(header);
    
    return 0;
}

static int map_image_memory(const BootImageHeader* header) {
    uint32_t code_pages = (header->code_size + PAGE_SIZE - 1) / PAGE_SIZE;
    uint32_t data_pages = (header->data_size + PAGE_SIZE - 1) / PAGE_SIZE;
    uint32_t bss_pages = (header->bss_size + PAGE_SIZE - 1) / PAGE_SIZE;
    
    /* Map code pages */
    for (uint32_t i = 0; i < code_pages; i++) {
        uint32_t phys_addr = allocate_physical_page();
        if (phys_addr == 0xFFFFFFFF) {
            return -1;  /* Out of memory */
        }
        
        mmu_map_page(i, phys_addr, 
            PAGE_PRESENT | PAGE_SRAM | PAGE_WAIT);
    }
    
    /* Map data and BSS pages */
    for (uint32_t i = 0; i < data_pages + bss_pages; i++) {
        uint32_t phys_addr = allocate_physical_page();
        if (phys_addr == 0xFFFFFFFF) {
            return -1;
        }
        
        mmu_map_page(32 + i, phys_addr, 
            PAGE_PRESENT | PAGE_SRAM | PAGE_WRITEABLE | PAGE_WAIT);
    }
    
    return 0;
}

#define DEBUG_UART_BASE 0xFFE0
#define DEBUG_BUFFER_SIZE 256

typedef struct {
    char buffer[DEBUG_BUFFER_SIZE];
    uint16_t head;
    uint16_t tail;
    uint8_t echo_enabled;
} DebugConsole;

#include "debug_console.h"

static const struct {
    const char* cmd;
    void (*handler)(int argc, char* argv[]);
    const char* help;
} debug_commands[] = {
    {"dump",    cmd_memory_dump,    "Display memory contents"},
    {"regs",    cmd_show_regs,     "Show CPU registers"},
    {"mmu",     cmd_show_mmu,      "Display MMU status"},
    {"trace",   cmd_set_trace,     "Set instruction trace"},
    {"break",   cmd_breakpoint,    "Set/clear breakpoint"},
    {"step",    cmd_single_step,   "Single step execution"},
    {NULL, NULL, NULL}
};

struct DebugState {
    uint32_t breakpoints[4];
    uint8_t bp_count;
    uint8_t trace_enabled;
    uint8_t single_step;
    uint16_t last_pc;
} debug_state;

void cmd_memory_dump(int argc, char* argv[]) {
    uint32_t addr = parse_hex_arg(argv[1]);
    uint16_t count = (argc > 2) ? parse_hex_arg(argv[2]) : 16;
    
    for (uint16_t i = 0; i < count; i += 16) {
        printf("%04X: ", addr + i);
        
        // Display hex values
        for (int j = 0; j < 16; j++) {
            printf("%02X ", read_memory_byte(addr + i + j));
            if (j == 7) printf("- ");
        }
        
        // Display ASCII representation
        printf("  |");
        for (int j = 0; j < 16; j++) {
            uint8_t byte = read_memory_byte(addr + i + j);
            printf("%c", (byte >= 32 && byte <= 126) ? byte : '.');
        }
        printf("|\n");
    }
}

void trace_instruction(uint16_t pc, uint16_t opcode) {
    static char disasm_buffer[64];
    
    if (!debug_state.trace_enabled) {
        return;
    }
    
    // Disassemble instruction
    disassemble_instruction(pc, opcode, disasm_buffer);
    
    // Display registers alongside instruction
    printf("%04X: %-32s  A=%04X B=%04X C=%04X SP=%04X\n",
           pc, disasm_buffer,
           get_register(REG_A),
           get_register(REG_B),
           get_register(REG_C),
           get_register(REG_SP));
}

int set_breakpoint(uint16_t addr) {
    if (debug_state.bp_count >= 4) {
        printf("Error: Maximum breakpoints reached\n");
        return -1;
    }
    
    // Save original instruction
    uint16_t original = read_memory_word(addr);
    
    // Insert breakpoint instruction (TRAP)
    write_memory_word(addr, 0xFFFF);
    
    // Store breakpoint info
    debug_state.breakpoints[debug_state.bp_count++] = 
        (addr << 16) | original;
        
    printf("Breakpoint set at %04X\n", addr);
    return 0;
}

#define ERR_SUCCESS          0x00
#define ERR_HARDWARE        0x01
#define ERR_MEMORY          0x02
#define ERR_TIMEOUT         0x03
#define ERR_CHECKSUM        0x04
#define ERR_INVALID_IMAGE   0x05
#define ERR_IO              0x06
#define ERR_MMU             0x07
#define ERR_PROTECTION      0x08

typedef struct error_info {
    uint8_t code;
    const char* message;
    uint8_t severity;
    uint8_t recoverable;
} error_info_t;

static const error_info_t error_table[] = {
    {ERR_SUCCESS,      "Operation successful",        0, 1},
    {ERR_HARDWARE,     "Hardware failure",           3, 0},
    {ERR_MEMORY,       "Memory allocation failed",   2, 1},
    {ERR_TIMEOUT,      "Operation timeout",          1, 1},
    {ERR_CHECKSUM,     "Checksum verification failed", 2, 1},
    {ERR_INVALID_IMAGE,"Invalid boot image format",  2, 1},
    {ERR_IO,          "I/O error",                  2, 1},
    {ERR_MMU,         "MMU configuration error",    3, 0},
    {ERR_PROTECTION,  "Protection violation",       3, 0},
    {0, NULL, 0, 0}
};

#include "errors.h"

#define MAX_ERROR_STACK 16
#define ERROR_LOG_SIZE  32

typedef struct {
    uint32_t timestamp;
    uint8_t error_code;
    uint16_t pc;
    uint8_t context;
} error_record_t;

static struct {
    error_record_t log[ERROR_LOG_SIZE];
    uint8_t log_head;
    uint8_t log_count;
    uint8_t error_stack[MAX_ERROR_STACK];
    uint8_t stack_ptr;
} error_context;

void handle_error(uint8_t error_code) {
    const error_info_t *info = NULL;
    
    // Find error info
    for(const error_info_t *ep = error_table; ep->message; ep++) {
        if(ep->code == error_code) {
            info = ep;
            break;
        }
    }
    
    if(!info) {
        printf("Unknown error code: 0x%02X\n", error_code);
        return;
    }
    
    // Log the error
    error_record_t *record = &error_context.log[error_context.log_head];
    record->timestamp = get_system_time();
    record->error_code = error_code;
    record->pc = get_current_pc();
    record->context = get_current_context();
    
    error_context.log_head = (error_context.log_head + 1) % ERROR_LOG_SIZE;
    if(error_context.log_count < ERROR_LOG_SIZE)
        error_context.log_count++;
    
    // Push to error stack
    if(error_context.stack_ptr < MAX_ERROR_STACK)
        error_context.error_stack[error_context.stack_ptr++] = error_code;
    
    // Handle based on severity
    switch(info->severity) {
        case 3: // Fatal
            printf("FATAL ERROR: %s\n", info->message);
            system_halt();
            break;
        case 2: // Severe
            printf("ERROR: %s\n", info->message);
            if(!info->recoverable)
                system_restart();
            break;
        case 1: // Warning
            printf("Warning: %s\n", info->message);
            break;
        default:
            break;
    }
}

#pragma once

#include <stdint.h>

typedef struct {
    struct {
        uint16_t base_memory;      // Base memory size in KB
        uint16_t extended_memory;   // Extended memory size in KB
        uint8_t  num_ide_drives;   // Number of IDE drives detected
        uint8_t  cf_card_present;  // CompactFlash card status
        uint8_t  uart_ports;       // Bitmap of available UART ports
    } hardware;
    
    struct {
        uint32_t load_address;     // Boot image load address
        uint8_t  auto_boot;        // Auto-boot flag
        uint8_t  boot_delay;       // Boot delay in seconds
        char     default_image[16];// Default boot image name
    } boot;
    
    struct {
        uint8_t  debug_level;      // Debug output level
        uint16_t console_baud;     // Console UART baud rate
        uint8_t  memory_wait;      // Memory wait states
        uint8_t  ide_mode;         // IDE interface mode
    } settings;
} SystemConfig;

extern SystemConfig system_config;

#include "system_config.h"

#define MEMORY_TEST_PATTERN 0x55AA
#define MAX_MEMORY_SIZE    0x20000  // 128KB

static int detect_memory_size(void) {
    uint16_t *mem_ptr = (uint16_t *)0;
    uint16_t size = 0;
    
    for(; size < MAX_MEMORY_SIZE; size += 1024) {
        mem_ptr[size/2] = MEMORY_TEST_PATTERN;
        if(mem_ptr[size/2] != MEMORY_TEST_PATTERN) {
            break;
        }
    }
    
    return size;
}

static void detect_uart_ports(void) {
    static const uint16_t uart_bases[] = {0xFFF0, 0xFFE0};
    uint8_t ports = 0;
    
    for(int i = 0; i < 2; i++) {
        // Write to scratch register
        outb(uart_bases[i] + 7, 0x55);
        if(inb(uart_bases[i] + 7) == 0x55) {
            ports |= (1 << i);
        }
    }
    
    system_config.hardware.uart_ports = ports;
}

int initialize_system_config(void) {
    // Clear configuration structure
    memset(&system_config, 0, sizeof(SystemConfig));
    
    // Detect memory size
    system_config.hardware.base_memory = detect_memory_size();
    
    // Detect UART ports
    detect_uart_ports();
    
    // Detect IDE/CF devices
    system_config.hardware.num_ide_drives = detect_ide_devices();
    system_config.hardware.cf_card_present = detect_cf_card();
    
    // Set default settings
    system_config.settings.console_baud = 9600;
    system_config.settings.debug_level = 1;
    system_config.settings.memory_wait = 1;
    
    return 0;
}

#define CONFIG_SECTOR_ADDR 0x1F000
#define CONFIG_MAGIC      0x4D31  // "M1"

typedef struct {
    uint16_t magic;
    uint16_t version;
    uint16_t checksum;
    SystemConfig config;
} ConfigBlock;

int save_system_config(void) {
    ConfigBlock block;
    
    block.magic = CONFIG_MAGIC;
    block.version = 1;
    memcpy(&block.config, &system_config, sizeof(SystemConfig));
    
    // Calculate checksum
    block.checksum = calculate_checksum(&block.config, sizeof(SystemConfig));
    
    // Write to storage
    return write_sector(CONFIG_SECTOR_ADDR, &block, sizeof(ConfigBlock));
}

int load_system_config(void) {
    ConfigBlock block;
    
    if(read_sector(CONFIG_SECTOR_ADDR, &block, sizeof(ConfigBlock)) != 0) {
        return -1;
    }
    
    if(block.magic != CONFIG_MAGIC || 
       block.checksum != calculate_checksum(&block.config, sizeof(SystemConfig))) {
        return -1;
    }
    
    memcpy(&system_config, &block.config, sizeof(SystemConfig));
    return 0;
}

#pragma once

typedef enum {
    DEVICE_UART,
    DEVICE_IDE,
    DEVICE_RTC,
    DEVICE_CF,
    DEVICE_MAX
} device_type_t;

typedef struct device_ops {
    int  (*init)(void *config);
    int  (*read)(void *buf, size_t count);
    int  (*write)(const void *buf, size_t count);
    int  (*ioctl)(int cmd, void *arg);
    void (*shutdown)(void);
} device_ops_t;

typedef struct device_driver {
    const char *name;
    device_type_t type;
    device_ops_t ops;
    void *private_data;
    uint8_t initialized;
} device_driver_t;

#include "driver_core.h"

#define MAX_DRIVERS 8

static struct {
    device_driver_t *drivers[MAX_DRIVERS];
    uint8_t driver_count;
} driver_manager;

int register_driver(device_driver_t *driver) {
    if (driver_manager.driver_count >= MAX_DRIVERS) {
        return -1;
    }
    
    driver_manager.drivers[driver_manager.driver_count++] = driver;
    return 0;
}

device_driver_t *get_driver(device_type_t type) {
    for (int i = 0; i < driver_manager.driver_count; i++) {
        if (driver_manager.drivers[i]->type == type) {
            return driver_manager.drivers[i];
        }
    }
    return NULL;
}

#include "driver_core.h"

#define UART_RX_BUFFER_SIZE 256
#define UART_TX_BUFFER_SIZE 256

typedef struct {
    uint16_t base_addr;
    uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
    uint8_t tx_buffer[UART_TX_BUFFER_SIZE];
    uint16_t rx_head, rx_tail;
    uint16_t tx_head, tx_tail;
} uart_private_t;

static int uart_init(void *config) {
    uart_private_t *priv = (uart_private_t *)config;
    
    // Initialize UART hardware
    outb(priv->base_addr + 3, 0x80);    // Enable DLAB
    outb(priv->base_addr + 0, 0x0C);    // Set baud rate divisor
    outb(priv->base_addr + 1, 0x00);
    outb(priv->base_addr + 3, 0x03);    // 8N1
    outb(priv->base_addr + 2, 0x07);    // Enable FIFOs
    
    return 0;
}

static device_driver_t uart_driver = {
    .name = "UART",
    .type = DEVICE_UART,
    .ops = {
        .init = uart_init,
        .read = uart_read,
        .write = uart_write,
        .ioctl = uart_ioctl,
        .shutdown = uart_shutdown
    }
};

#define NUM_INTERRUPTS    8
#define VECTOR_TABLE_BASE 0x0000

typedef struct {
    void (*handler)(void);
    uint8_t priority;
    uint8_t enabled;
    uint32_t count;
    const char* name;
} interrupt_vector_t;

static interrupt_vector_t interrupt_vectors[NUM_INTERRUPTS] = {
    { nmi_handler,     0, 1, 0, "NMI"     },
    { timer_handler,   1, 1, 0, "Timer"   },
    { uart0_handler,   2, 1, 0, "UART0"   },
    { uart1_handler,   2, 1, 0, "UART1"   },
    { ide_handler,     3, 1, 0, "IDE"     },
    { rtc_handler,     4, 1, 0, "RTC"     },
    { fault_handler,   0, 1, 0, "Fault"   },
    { trap_handler,    0, 1, 0, "Trap"    }
};

#define TIMER_BASE      0xFFD0
#define TIMER_COUNT     (TIMER_BASE + 0)
#define TIMER_CONTROL   (TIMER_BASE + 2)
#define TIMER_STATUS    (TIMER_BASE + 4)

#define TIMER_ENABLE    0x01
#define TIMER_INTERRUPT 0x02
#define TIMER_RELOAD    0x04

typedef struct {
    uint16_t reload_value;
    uint32_t tick_count;
    void (*callback)(void);
} timer_context_t;

static timer_context_t timer_ctx;

void init_timer(uint16_t reload_value, void (*callback)(void)) {
    timer_ctx.reload_value = reload_value;
    timer_ctx.callback = callback;
    timer_ctx.tick_count = 0;
    
    // Configure timer hardware
    outw(TIMER_COUNT, reload_value);
    outw(TIMER_CONTROL, TIMER_ENABLE | TIMER_INTERRUPT | TIMER_RELOAD);
}

void timer_handler(void) {
    timer_ctx.tick_count++;
    
    // Clear interrupt
    outb(TIMER_STATUS, 0);
    
    if (timer_ctx.callback) {
        timer_ctx.callback();
    }
}

#define INT_CTRL_BASE   0xFFC0
#define INT_MASK        (INT_CTRL_BASE + 0)
#define INT_STATUS      (INT_CTRL_BASE + 2)
#define INT_ACK         (INT_CTRL_BASE + 4)

void enable_interrupt(uint8_t irq) {
    uint16_t mask = inw(INT_MASK);
    mask |= (1 << irq);
    outw(INT_MASK, mask);
}

void disable_interrupt(uint8_t irq) {
    uint16_t mask = inw(INT_MASK);
    mask &= ~(1 << irq);
    outw(INT_MASK, mask);
}

void acknowledge_interrupt(uint8_t irq) {
    outw(INT_ACK, 1 << irq);
}

// Main interrupt dispatcher
void interrupt_dispatch(void) {
    uint16_t status = inw(INT_STATUS);
    
    for (int i = 0; i < NUM_INTERRUPTS; i++) {
        if (status & (1 << i)) {
            if (interrupt_vectors[i].enabled && interrupt_vectors[i].handler) {
                interrupt_vectors[i].count++;
                interrupt_vectors[i].handler();
            }
            acknowledge_interrupt(i);
        }
    }
}

typedef enum {
    BOOT_STATE_INIT,
    BOOT_STATE_HARDWARE_DETECT,
    BOOT_STATE_MEMORY_TEST,
    BOOT_STATE_LOAD_CONFIG,
    BOOT_STATE_MOUNT_STORAGE,
    BOOT_STATE_LOAD_IMAGE,
    BOOT_STATE_EXECUTE
} boot_state_t;

typedef struct {
    boot_state_t current_state;
    uint8_t retry_count;
    uint32_t start_time;
    char error_message[64];
} boot_context_t;

#include "boot_manager.h"
#include "hardware_detect.h"
#include "memory_test.h"
#include "storage.h"

static boot_context_t boot_ctx;

int execute_boot_sequence(void) {
    int status = 0;
    
    // Initialize boot context
    boot_ctx.current_state = BOOT_STATE_INIT;
    boot_ctx.retry_count = 0;
    boot_ctx.start_time = get_rtc_time();
    
    while (boot_ctx.current_state != BOOT_STATE_EXECUTE) {
        switch (boot_ctx.current_state) {
            case BOOT_STATE_INIT:
                status = initialize_core_hardware();
                if (status == 0) {
                    boot_ctx.current_state = BOOT_STATE_HARDWARE_DETECT;
                }
                break;
                
            case BOOT_STATE_HARDWARE_DETECT:
                status = detect_hardware_configuration();
                if (status == 0) {
                    boot_ctx.current_state = BOOT_STATE_MEMORY_TEST;
                }
                break;
                
            case BOOT_STATE_MEMORY_TEST:
                status = perform_memory_test();
                if (status == 0) {
                    boot_ctx.current_state = BOOT_STATE_LOAD_CONFIG;
                }
                break;
                
            case BOOT_STATE_LOAD_CONFIG:
                status = load_system_configuration();
                if (status == 0) {
                    boot_ctx.current_state = BOOT_STATE_MOUNT_STORAGE;
                }
                break;
                
            case BOOT_STATE_MOUNT_STORAGE:
                status = mount_boot_storage();
                if (status == 0) {
                    boot_ctx.current_state = BOOT_STATE_LOAD_IMAGE;
                }
                break;
                
            case BOOT_STATE_LOAD_IMAGE:
                status = load_boot_image();
                if (status == 0) {
                    boot_ctx.current_state = BOOT_STATE_EXECUTE;
                }
                break;
                
            default:
                sprintf(boot_ctx.error_message, "Invalid boot state: %d", 
                        boot_ctx.current_state);
                return -1;
        }
        
        if (status != 0) {
            handle_boot_error(status);
            if (++boot_ctx.retry_count >= MAX_BOOT_RETRIES) {
                return -1;
            }
        }
    }
    
    return 0;
}

#define SECTOR_SIZE     512
#define MAX_DEVICES     4
#define MAX_PARTITIONS  16

typedef enum {
    STORAGE_IDE,
    STORAGE_CF,
    STORAGE_ROM
} storage_type_t;

typedef struct {
    uint32_t start_sector;
    uint32_t num_sectors;
    uint8_t  type;
    uint8_t  bootable;
} partition_entry_t;

typedef struct storage_device {
    storage_type_t type;
    uint8_t  id;
    uint32_t sector_count;
    uint16_t sector_size;
    
    // Device operations
    int (*read_sector)(struct storage_device *dev, uint32_t sector, void *buffer);
    int (*write_sector)(struct storage_device *dev, uint32_t sector, const void *buffer);
    int (*ioctl)(struct storage_device *dev, int cmd, void *arg);
    
    // Partition table
    partition_entry_t partitions[MAX_PARTITIONS];
    uint8_t partition_count;
    
    // Device-specific data
    void *private_data;
} storage_device_t;

#include "storage.h"

static struct {
    storage_device_t *devices[MAX_DEVICES];
    uint8_t device_count;
    storage_device_t *boot_device;
} storage_manager;

int register_storage_device(storage_device_t *device) {
    if (storage_manager.device_count >= MAX_DEVICES) {
        return -1;
    }
    
    // Initialize device
    if (scan_partitions(device) != 0) {
        return -2;
    }
    
    storage_manager.devices[storage_manager.device_count++] = device;
    
    // Set as boot device if bootable partition found
    for (int i = 0; i < device->partition_count; i++) {
        if (device->partitions[i].bootable) {
            storage_manager.boot_device = device;
            break;
        }
    }
    
    return 0;
}

int read_storage_sectors(storage_device_t *dev, 
                        uint32_t start_sector,
                        uint32_t count,
                        void *buffer) {
    if (!dev || !dev->read_sector) {
        return -1;
    }
    
    uint8_t *buf = (uint8_t *)buffer;
    for (uint32_t i = 0; i < count; i++) {
        int status = dev->read_sector(dev, start_sector + i, 
                                    buf + (i * dev->sector_size));
        if (status != 0) {
            return status;
        }
    }
    
    return 0;
}

#define MBR_SIGNATURE   0xAA55
#define PARTITION_ENTRY_OFFSET 0x1BE

typedef struct {
    uint8_t  boot_flag;
    uint8_t  start_head;
    uint16_t start_sector_cyl;
    uint8_t  type;
    uint8_t  end_head;
    uint16_t end_sector_cyl;
    uint32_t start_sector;
    uint32_t num_sectors;
} __attribute__((packed)) mbr_partition_t;

int scan_partitions(storage_device_t *dev) {
    uint8_t mbr[SECTOR_SIZE];
    mbr_partition_t *part;
    
    // Read MBR
    if (dev->read_sector(dev, 0, mbr) != 0) {
        return -1;
    }
    
    // Verify MBR signature
    if (*(uint16_t *)&mbr[510] != MBR_SIGNATURE) {
        return -2;
    }
    
    // Parse partition entries
    dev->partition_count = 0;
    part = (mbr_partition_t *)&mbr[PARTITION_ENTRY_OFFSET];
    
    for (int i = 0; i < 4; i++, part++) {
        if (part->type == 0) {
            continue;
        }
        
        dev->partitions[dev->partition_count].start_sector = part->start_sector;
        dev->partitions[dev->partition_count].num_sectors = part->num_sectors;
        dev->partitions[dev->partition_count].type = part->type;
        dev->partitions[dev->partition_count].bootable = 
            (part->boot_flag == 0x80);
            
        dev->partition_count++;
    }
    
    return 0;
}

typedef struct command_handler {
    const char* command;        // Command string
    const char* description;    // Help text
    uint8_t min_args;          // Minimum arguments required
    uint8_t max_args;          // Maximum arguments allowed
    int (*handler)(int argc, char* argv[]);  // Command function
    uint8_t requires_auth;     // Whether authentication is required
} command_handler_t;

#define MAX_COMMAND_LENGTH 32
#define MAX_ARGS 8
#define COMMAND_BUFFER_SIZE 256

static const command_handler_t command_table[] = {
    {
        .command = "boot",
        .description = "Boot specified image",
        .min_args = 1,
        .max_args = 2,
        .handler = cmd_boot_image,
        .requires_auth = 1
    },
    {
        .command = "list",
        .description = "List available boot images",
        .min_args = 0,
        .max_args = 0,
        .handler = cmd_list_images,
        .requires_auth = 0
    },
    {
        .command = "set",
        .description = "Set configuration parameter",
        .min_args = 2,
        .max_args = 2,
        .handler = cmd_set_config,
        .requires_auth = 1
    },
    {
        .command = "help",
        .description = "Show available commands",
        .min_args = 0,
        .max_args = 1,
        .handler = cmd_show_help,
        .requires_auth = 0
    },
    { NULL, NULL, 0, 0, NULL, 0 }  // Terminator
};

int process_command(const char* input) {
    char buffer[COMMAND_BUFFER_SIZE];
    char* argv[MAX_ARGS];
    int argc = 0;
    
    // Copy input to avoid modifying original
    strncpy(buffer, input, COMMAND_BUFFER_SIZE);
    buffer[COMMAND_BUFFER_SIZE - 1] = '\0';
    
    // Parse command line
    char* token = strtok(buffer, " \t");
    while (token && argc < MAX_ARGS) {
        argv[argc++] = token;
        token = strtok(NULL, " \t");
    }
    
    if (argc == 0) {
        return 0;  // Empty command
    }
    
    // Find command handler
    for (const command_handler_t* cmd = command_table; cmd->command; cmd++) {
        if (strcmp(argv[0], cmd->command) == 0) {
            // Check argument count
            if (argc - 1 < cmd->min_args || argc - 1 > cmd->max_args) {
                printf("Error: Invalid number of arguments\n");
                printf("Usage: %s %s\n", cmd->command, cmd->description);
                return -1;
            }
            
            // Check authentication if required
            if (cmd->requires_auth && !is_authenticated()) {
                printf("Error: Authentication required\n");
                return -1;
            }
            
            // Execute command
            return cmd->handler(argc, argv);
        }
    }
    
    printf("Error: Unknown command '%s'\n", argv[0]);
    return -1;
}

#define AUTH_TOKEN_LENGTH 32
#define MAX_PASSWORD_LENGTH 64
#define SALT_LENGTH 16

typedef struct {
    uint8_t token[AUTH_TOKEN_LENGTH];
    uint32_t creation_time;
    uint32_t expiry_time;
} auth_token_t;

typedef struct {
    uint8_t hash[AUTH_TOKEN_LENGTH];
    uint8_t salt[SALT_LENGTH];
    uint8_t attempts;
    uint32_t lockout_until;
} auth_config_t;

#include "auth.h"
#include "crypto/sha256.h"

#define MAX_LOGIN_ATTEMPTS 3
#define LOCKOUT_DURATION 300  // 5 minutes in seconds

static auth_config_t auth_config;
static auth_token_t current_token;
static uint8_t is_authenticated_flag = 0;

int authenticate(const char* password) {
    uint8_t hash[AUTH_TOKEN_LENGTH];
    uint32_t current_time = get_rtc_time();
    
    // Check lockout
    if (auth_config.lockout_until > current_time) {
        printf("Account is locked. Try again in %d seconds\n", 
               auth_config.lockout_until - current_time);
        return -1;
    }
    
    // Calculate password hash with salt
    sha256_context ctx;
    sha256_init(&ctx);
    sha256_update(&ctx, (uint8_t*)password, strlen(password));
    sha256_update(&ctx, auth_config.salt, SALT_LENGTH);
    sha256_final(&ctx, hash);
    
    // Verify hash
    if (memcmp(hash, auth_config.hash, AUTH_TOKEN_LENGTH) == 0) {
        // Success - generate new auth token
        generate_random_bytes(current_token.token, AUTH_TOKEN_LENGTH);
        current_token.creation_time = current_time;
        current_token.expiry_time = current_time + 3600;  // 1 hour validity
        
        auth_config.attempts = 0;
        is_authenticated_flag = 1;
        return 0;
    }
    
    // Failed attempt
    auth_config.attempts++;
    if (auth_config.attempts >= MAX_LOGIN_ATTEMPTS) {
        auth_config.lockout_until = current_time + LOCKOUT_DURATION;
        auth_config.attempts = 0;
    }
    
    return -1;
}

#include "auth.h"

void generate_random_bytes(uint8_t* buffer, size_t length) {
    // Use hardware RTC as entropy source
    uint32_t rtc_value;
    uint8_t entropy[4];
    
    for (size_t i = 0; i < length; i++) {
        if (i % 4 == 0) {
            rtc_value = get_rtc_time();
            memcpy(entropy, &rtc_value, 4);
        }
        buffer[i] = entropy[i % 4] ^ (i * 0x5A);  // Simple mixing function
    }
}

int change_password(const char* old_password, const char* new_password) {
    if (!is_authenticated() || strlen(new_password) > MAX_PASSWORD_LENGTH) {
        return -1;
    }
    
    // Verify old password first
    if (authenticate(old_password) != 0) {
        return -1;
    }
    
    // Generate new salt
    generate_random_bytes(auth_config.salt, SALT_LENGTH);
    
    // Hash new password
    sha256_context ctx;
    sha256_init(&ctx);
    sha256_update(&ctx, (uint8_t*)new_password, strlen(new_password));
    sha256_update(&ctx, auth_config.salt, SALT_LENGTH);
    sha256_final(&ctx, auth_config.hash);
    
    // Save configuration
    save_auth_config();
    
    return 0;
}

#pragma once
#include <stdint.h>

typedef enum {
    HAL_SUCCESS = 0,
    HAL_ERROR_INVALID_PARAM = -1,
    HAL_ERROR_NOT_INITIALIZED = -2,
    HAL_ERROR_HARDWARE = -3,
    HAL_ERROR_TIMEOUT = -4
} hal_status_t;

/* Core HAL interface functions */
typedef struct {
    /* System Control */
    void (*reset_system)(void);
    void (*halt_system)(void);
    void (*delay_ms)(uint32_t ms);
    
    /* Memory Management */
    void* (*mem_map)(uint32_t phys_addr, size_t size);
    void (*mem_unmap)(void* addr);
    
    /* Interrupt Management */
    void (*enable_irq)(uint8_t irq);
    void (*disable_irq)(uint8_t irq);
    
    /* I/O Operations */
    uint8_t (*read_io8)(uint16_t port);
    void (*write_io8)(uint16_t port, uint8_t value);
    uint16_t (*read_io16)(uint16_t port);
    void (*write_io16)(uint16_t port, uint16_t value);
} hal_ops_t;

#include "hal.h"

/* Hardware-specific definitions */
#define MAGIC1_CONTROL_REG   0xFFF0
#define MAGIC1_STATUS_REG    0xFFF2
#define MAGIC1_RESET_BIT     0x01
#define MAGIC1_HALT_BIT      0x02

static hal_ops_t magic1_hal_ops;

static void magic1_reset_system(void) {
    /* Set reset bit in control register */
    uint16_t ctrl = read_io16(MAGIC1_CONTROL_REG);
    write_io16(MAGIC1_CONTROL_REG, ctrl | MAGIC1_RESET_BIT);
    
    /* System should reset, but if we get here, halt */
    while(1) { }
}

static void magic1_delay_ms(uint32_t ms) {
    uint32_t cycles = ms * (CLOCK_FREQUENCY / 1000);
    while(cycles--) {
        __asm__ volatile("nop");
    }
}

/* Initialize HAL operations structure */
void hal_init(void) {
    magic1_hal_ops.reset_system = magic1_reset_system;
    magic1_hal_ops.halt_system = magic1_halt_system;
    magic1_hal_ops.delay_ms = magic1_delay_ms;
    magic1_hal_ops.mem_map = magic1_mem_map;
    magic1_hal_ops.mem_unmap = magic1_mem_unmap;
    magic1_hal_ops.enable_irq = magic1_enable_irq;
    magic1_hal_ops.disable_irq = magic1_disable_irq;
    magic1_hal_ops.read_io8 = magic1_read_io8;
    magic1_hal_ops.write_io8 = magic1_write_io8;
    magic1_hal_ops.read_io16 = magic1_read_io16;
    magic1_hal_ops.write_io16 = magic1_write_io16;
}

#include "unity.h"
#include "hal.h"

void setUp(void) {
    hal_init();
}

void tearDown(void) {
    /* Nothing to clean up */
}

void test_io_operations(void) {
    /* Test 8-bit I/O */
    write_io8(0xFF00, 0x55);
    TEST_ASSERT_EQUAL_UINT8(0x55, read_io8(0xFF00));
    
    /* Test 16-bit I/O */
    write_io16(0xFF02, 0xAA55);
    TEST_ASSERT_EQUAL_UINT16(0xAA55, read_io16(0xFF02));
}

void test_interrupt_management(void) {
    /* Test IRQ enable/disable */
    enable_irq(1);
    TEST_ASSERT_BIT_HIGH(read_io16(MAGIC1_STATUS_REG), 1);
    
    disable_irq(1);
    TEST_ASSERT_BIT_LOW(read_io16(MAGIC1_STATUS_REG), 1);
}

#pragma once
#include <stdint.h>

/* System power states */
typedef enum {
    POWER_STATE_RUN,      // Normal operation
    POWER_STATE_IDLE,     // CPU idle, peripherals active
    POWER_STATE_STANDBY,  // Low power mode, quick wake
    POWER_STATE_SHUTDOWN  // Full power down
} power_state_t;

/* Clock configuration */
typedef struct {
    uint8_t  pll_multiplier;  // 1-16
    uint8_t  pll_divider;     // 1-8
    uint8_t  cpu_divider;     // 1-8
    uint8_t  periph_divider;  // 1-8
    uint32_t target_freq;     // Desired CPU frequency
} clock_config_t;

#include "power_mgmt.h"

#define POWER_CTRL_REG    0xFFF4
#define CLOCK_CTRL_REG    0xFFF6
#define STATUS_REG        0xFFF8

#define PWR_MODE_MASK     0x03
#define PLL_LOCK_BIT      0x80
#define CLK_STABLE_BIT    0x40

static power_state_t current_power_state = POWER_STATE_RUN;
static clock_config_t current_clock_config;

int set_power_state(power_state_t new_state) {
    uint16_t ctrl_reg;
    
    if (new_state == current_power_state) {
        return 0;  // Already in requested state
    }
    
    // Read current control register
    ctrl_reg = read_io16(POWER_CTRL_REG);
    
    // Clear power mode bits
    ctrl_reg &= ~PWR_MODE_MASK;
    
    // Set new power mode
    switch (new_state) {
        case POWER_STATE_RUN:
            ctrl_reg |= 0x00;
            break;
            
        case POWER_STATE_IDLE:
            ctrl_reg |= 0x01;
            break;
            
        case POWER_STATE_STANDBY:
            ctrl_reg |= 0x02;
            break;
            
        case POWER_STATE_SHUTDOWN:
            ctrl_reg |= 0x03;
            break;
            
        default:
            return -1;
    }
    
    // Update control register
    write_io16(POWER_CTRL_REG, ctrl_reg);
    
    // Wait for state change to complete
    while ((read_io16(STATUS_REG) & PWR_MODE_MASK) != 
           (ctrl_reg & PWR_MODE_MASK)) {
        // Timeout check could be added here
    }
    
    current_power_state = new_state;
    return 0;
}

#include "power_mgmt.h"

int configure_system_clock(const clock_config_t* config) {
    uint16_t clock_ctrl;
    uint32_t timeout = 1000;  // Timeout counter
    
    // Validate configuration
    if (!config || config->pll_multiplier > 16 || 
        config->pll_divider > 8 || config->cpu_divider > 8) {
        return -1;
    }
    
    // Build clock control value
    clock_ctrl = ((config->pll_multiplier - 1) << 12) |
                ((config->pll_divider - 1) << 9) |
                ((config->cpu_divider - 1) << 6) |
                ((config->periph_divider - 1) << 3);
                
    // Update clock control register
    write_io16(CLOCK_CTRL_REG, clock_ctrl);
    
    // Wait for PLL lock and clock stabilization
    while (timeout--) {
        if ((read_io16(STATUS_REG) & (PLL_LOCK_BIT | CLK_STABLE_BIT)) ==
            (PLL_LOCK_BIT | CLK_STABLE_BIT)) {
            memcpy(&current_clock_config, config, sizeof(clock_config_t));
            return 0;
        }
    }
    
    return -1;  // Timeout waiting for clock stabilization
}

#define MAGIC_NUMBER     0x4D31    // "M1"
#define IMAGE_VERSION    0x0001
#define MAX_IMAGE_NAME   32
#define MAX_SIGNATURES   4

typedef struct {
    uint16_t magic;              // Magic number identifier
    uint16_t version;           // Image format version
    uint32_t total_size;        // Total image size including header
    uint32_t entry_point;       // Entry point address
    uint32_t load_address;      // Load address
    uint32_t code_size;         // Size of code segment
    uint32_t data_size;         // Size of data segment
    uint32_t bss_size;          // Size of BSS segment
    uint32_t symbol_offset;     // Offset to symbol table
    uint32_t reloc_offset;      // Offset to relocation table
    uint8_t  flags;             // Image flags
    uint8_t  cpu_type;          // Target CPU type
    char     name[MAX_IMAGE_NAME]; // Image name
    uint8_t  signatures[MAX_SIGNATURES][64]; // Digital signatures
    uint32_t checksum;          // CRC32 of image excluding header
} __attribute__((packed)) boot_image_header_t;

#include "boot_image.h"
#include "crypto/crc32.h"
#include "crypto/sha256.h"

static const uint8_t public_key[32] = {
    0x55, 0xAA, /* ... public key data ... */
};

int verify_boot_image(const void* image_data, size_t size) {
    const boot_image_header_t* header = (const boot_image_header_t*)image_data;
    uint32_t computed_crc;
    
    // Verify minimum size
    if (size < sizeof(boot_image_header_t)) {
        return -1;
    }
    
    // Check magic number and version
    if (header->magic != MAGIC_NUMBER || 
        header->version != IMAGE_VERSION) {
        return -2;
    }
    
    // Verify total size
    if (size < header->total_size) {
        return -3;
    }
    
    // Calculate and verify checksum
    computed_crc = crc32(0, 
        (uint8_t*)image_data + sizeof(boot_image_header_t),
        header->total_size - sizeof(boot_image_header_t));
        
    if (computed_crc != header->checksum) {
        return -4;
    }
    
    // Verify digital signatures if present
    if (header->flags & IMAGE_FLAG_SIGNED) {
        if (verify_signatures(header) != 0) {
            return -5;
        }
    }
    
    return 0;
}

#include "boot_image.h"
#include "memory/mmu.h"

int load_boot_image(const void* image_data) {
    const boot_image_header_t* header = (const boot_image_header_t*)image_data;
    const uint8_t* data = (const uint8_t*)image_data;
    void* load_addr;
    
    // First verify the image
    if (verify_boot_image(image_data, header->total_size) != 0) {
        return -1;
    }
    
    // Allocate and map memory
    load_addr = mmu_map_region(header->load_address, 
                              header->total_size,
                              MMU_FLAG_READ | MMU_FLAG_WRITE | MMU_FLAG_EXEC);
                              
    if (!load_addr) {
        return -2;
    }
    
    // Copy code segment
    memcpy((void*)header->load_address,
           data + sizeof(boot_image_header_t),
           header->code_size);
           
    // Copy data segment
    memcpy((void*)(header->load_address + header->code_size),
           data + sizeof(boot_image_header_t) + header->code_size,
           header->data_size);
           
    // Clear BSS segment
    memset((void*)(header->load_address + header->code_size + header->data_size),
           0,
           header->bss_size);
           
    // Process relocations if present
    if (header->reloc_offset) {
        process_relocations(header);
    }
    
    return 0;
}

#define INIT_FLAG_MMU_ENABLED    (1 << 0)
#define INIT_FLAG_CACHE_ENABLED  (1 << 1)
#define INIT_FLAG_INTERRUPTS_ON  (1 << 2)

typedef enum {
    BOOT_PHASE_RESET,
    BOOT_PHASE_EARLY_INIT,
    BOOT_PHASE_HARDWARE_INIT,
    BOOT_PHASE_MEMORY_INIT,
    BOOT_PHASE_DEVICE_INIT,
    BOOT_PHASE_FINAL_INIT
} boot_phase_t;

typedef struct {
    boot_phase_t current_phase;
    uint32_t flags;
    uint32_t boot_time;
    uint32_t error_code;
} boot_state_t;

static boot_state_t boot_state = {
    .current_phase = BOOT_PHASE_RESET,
    .flags = 0,
    .boot_time = 0,
    .error_code = 0
};

void boot_init(void) {
    // Early hardware initialization
    early_hw_init();
    boot_state.current_phase = BOOT_PHASE_EARLY_INIT;
    
    // Initialize memory subsystem
    if (init_memory() != 0) {
        boot_state.error_code = ERR_MEMORY_INIT;
        panic();
    }
    boot_state.current_phase = BOOT_PHASE_MEMORY_INIT;
    
    // Enable MMU
    if (mmu_init() == 0) {
        boot_state.flags |= INIT_FLAG_MMU_ENABLED;
    }
    
    // Initialize essential devices
    init_uart();
    init_timer();
    init_interrupt_controller();
    
    boot_state.current_phase = BOOT_PHASE_DEVICE_INIT;
    
    // Enable interrupts
    sti();
    boot_state.flags |= INIT_FLAG_INTERRUPTS_ON;
    
    // Jump to main bootloader code
    bootloader_main();
}

#include <stdint.h>

/* Memory protection flags */
#define MEM_PROT_READ    (1 << 0)
#define MEM_PROT_WRITE   (1 << 1)
#define MEM_PROT_EXEC    (1 << 2)

/* Memory type definitions */
#define MEM_TYPE_RAM     0
#define MEM_TYPE_ROM     1
#define MEM_TYPE_DEVICE  2

struct memory_region {
    uint32_t start;          /* Start address */
    uint32_t size;           /* Region size */
    uint8_t  type;          /* Memory type */
    uint8_t  protection;    /* Protection flags */
    uint8_t  cacheable;     /* Cache enable flag */
    char     name[16];      /* Region name */
};

#define CACHE_CTRL_REG   0xFFF2
#define CACHE_FLUSH_BIT  0x01
#define CACHE_ENABLE_BIT 0x02

void flush_cache(void) {
    uint16_t ctrl;
    
    /* Read current cache control */
    ctrl = read_io16(CACHE_CTRL_REG);
    
    /* Set flush bit */
    write_io16(CACHE_CTRL_REG, ctrl | CACHE_FLUSH_BIT);
    
    /* Wait for flush to complete */
    while(read_io16(CACHE_CTRL_REG) & CACHE_FLUSH_BIT) {
        /* Busy wait */
    }
}

int configure_cache(int enable) {
    uint16_t ctrl = read_io16(CACHE_CTRL_REG);
    
    if(enable) {
        ctrl |= CACHE_ENABLE_BIT;
    } else {
        ctrl &= ~CACHE_ENABLE_BIT;
    }
    
    write_io16(CACHE_CTRL_REG, ctrl);
    return 0;
}

#define MAX_MEMORY_REGIONS 16

static struct memory_region regions[MAX_MEMORY_REGIONS];
static int num_regions = 0;

int register_memory_region(const struct memory_region *region) {
    if(num_regions >= MAX_MEMORY_REGIONS) {
        return -1;
    }
    
    /* Check for overlap with existing regions */
    for(int i = 0; i < num_regions; i++) {
        if((region->start < (regions[i].start + regions[i].size)) &&
           ((region->start + region->size) > regions[i].start)) {
            return -2;
        }
    }
    
    /* Add new region */
    memcpy(&regions[num_regions], region, sizeof(struct memory_region));
    num_regions++;
    
    return 0;
}

#define MAX_INTERRUPTS 16
#define IRQ_LEVELS     8

/* Interrupt vector definitions */
#define IRQ_NMI        0   /* Non-maskable interrupt */
#define IRQ_TIMER      1   /* System timer */
#define IRQ_UART0      2   /* Primary UART */
#define IRQ_UART1      3   /* Secondary UART */
#define IRQ_IDE        4   /* IDE interface */
#define IRQ_RTC        5   /* Real-time clock */
#define IRQ_FAULT      6   /* CPU fault */
#define IRQ_TRAP       7   /* Software trap */

/* Interrupt priority levels */
typedef enum {
    IPL_NONE = 0,
    IPL_LOW  = 1,
    IPL_MED  = 4,
    IPL_HIGH = 6,
    IPL_NMI  = 7
} ipl_t;

#include "interrupts.h"

typedef struct {
    void (*handler)(void);
    ipl_t priority;
    uint32_t count;
    const char *name;
} vector_entry_t;

static vector_entry_t vector_table[MAX_INTERRUPTS] = {
    [IRQ_NMI]   = { nmi_handler,   IPL_NMI,  0, "NMI" },
    [IRQ_TIMER] = { timer_handler, IPL_HIGH, 0, "Timer" },
    [IRQ_UART0] = { uart0_handler, IPL_MED,  0, "UART0" },
    [IRQ_UART1] = { uart1_handler, IPL_MED,  0, "UART1" },
    [IRQ_IDE]   = { ide_handler,   IPL_LOW,  0, "IDE" },
    [IRQ_RTC]   = { rtc_handler,   IPL_LOW,  0, "RTC" },
    [IRQ_FAULT] = { fault_handler, IPL_NMI,  0, "Fault" },
    [IRQ_TRAP]  = { trap_handler,  IPL_HIGH, 0, "Trap" }
};

/* Initialize vector table in hardware */
void init_vectors(void) {
    for(int i = 0; i < MAX_INTERRUPTS; i++) {
        if(vector_table[i].handler) {
            write_vector(i, vector_table[i].handler);
            set_vector_priority(i, vector_table[i].priority);
        }
    }
}

#define INT_CTRL_BASE   0xFFC0
#define INT_MASK_REG    (INT_CTRL_BASE + 0)
#define INT_STATUS_REG  (INT_CTRL_BASE + 2)
#define INT_ACK_REG     (INT_CTRL_BASE + 4)
#define INT_PRIO_REG    (INT_CTRL_BASE + 6)

static uint16_t interrupt_mask = 0;
static uint8_t current_ipl = IPL_NONE;

void enable_interrupt(uint8_t irq) {
    if(irq < MAX_INTERRUPTS) {
        interrupt_mask |= (1 << irq);
        write_io16(INT_MASK_REG, interrupt_mask);
    }
}

void set_ipl(uint8_t level) {
    current_ipl = level;
    write_io16(INT_PRIO_REG, level);
}

void interrupt_dispatch(void) {
    uint16_t active = read_io16(INT_STATUS_REG);
    
    for(int i = 0; i < MAX_INTERRUPTS; i++) {
        if(active & (1 << i)) {
            if(vector_table[i].handler && 
               vector_table[i].priority > current_ipl) {
                vector_table[i].count++;
                vector_table[i].handler();
            }
            write_io16(INT_ACK_REG, 1 << i);
        }
    }
}

#include <stdint.h>

typedef enum {
    DRIVER_STATUS_OK = 0,
    DRIVER_STATUS_ERROR = -1,
    DRIVER_STATUS_TIMEOUT = -2,
    DRIVER_STATUS_NOT_SUPPORTED = -3
} driver_status_t;

typedef struct device_driver {
    const char* name;
    uint32_t base_address;
    uint32_t irq_number;
    
    /* Driver operations */
    int (*init)(struct device_driver* driver);
    int (*read)(struct device_driver* driver, void* buffer, size_t size);
    int (*write)(struct device_driver* driver, const void* buffer, size_t size);
    int (*ioctl)(struct device_driver* driver, uint32_t cmd, void* arg);
    void (*irq_handler)(struct device_driver* driver);
    void (*shutdown)(struct device_driver* driver);
    
    /* Private data */
    void* private_data;
} device_driver_t;

#include "driver_interface.h"

#define UART_RBR 0x00   /* Receive Buffer Register */
#define UART_THR 0x00   /* Transmit Holding Register */
#define UART_IER 0x01   /* Interrupt Enable Register */
#define UART_FCR 0x02   /* FIFO Control Register */
#define UART_LCR 0x03   /* Line Control Register */
#define UART_LSR 0x05   /* Line Status Register */

typedef struct {
    uint8_t tx_fifo[16];
    uint8_t rx_fifo[16];
    uint8_t tx_head;
    uint8_t tx_tail;
    uint8_t rx_head;
    uint8_t rx_tail;
} uart_private_t;

static int uart_init(device_driver_t* driver) {
    uint16_t base = driver->base_address;
    
    /* Initialize UART hardware */
    outb(base + UART_LCR, 0x80);    /* Enable DLAB */
    outb(base + UART_RBR, 0x0C);    /* Baud rate divisor */
    outb(base + UART_IER, 0x00);
    outb(base + UART_LCR, 0x03);    /* 8N1 */
    outb(base + UART_FCR, 0x07);    /* Enable and clear FIFOs */
    
    /* Allocate private data */
    driver->private_data = malloc(sizeof(uart_private_t));
    memset(driver->private_data, 0, sizeof(uart_private_t));
    
    return DRIVER_STATUS_OK;
}

#include "driver_interface.h"

#define IDE_DATA    0x00
#define IDE_ERROR   0x01
#define IDE_STATUS  0x07
#define IDE_COMMAND 0x07

typedef struct {
    uint8_t is_present;
    uint8_t is_master;
    uint16_t cylinders;
    uint16_t heads;
    uint16_t sectors;
} ide_private_t;

static int ide_init(device_driver_t* driver) {
    uint16_t base = driver->base_address;
    ide_private_t* priv;
    
    /* Allocate private data */
    driver->private_data = malloc(sizeof(ide_private_t));
    priv = (ide_private_t*)driver->private_data;
    
    /* Detect drive presence */
    outb(base + IDE_COMMAND, 0xEC);  /* IDENTIFY command */
    if (inb(base + IDE_STATUS) == 0) {
        priv->is_present = 0;
        return DRIVER_STATUS_ERROR;
    }
    
    /* Read identification data */
    for (int i = 0; i < 256; i++) {
        uint16_t data = inw(base + IDE_DATA);
        /* Process identification data */
    }
    
    return DRIVER_STATUS_OK;
}

#define FS_MAX_PATH      256
#define FS_MAX_NAME      64
#define FS_MAX_OPEN      8
#define FS_SECTOR_SIZE   512

typedef enum {
    FS_TYPE_NONE = 0,
    FS_TYPE_FAT16,
    FS_TYPE_FAT32,
    FS_TYPE_M1FS
} fs_type_t;

typedef struct {
    char     name[FS_MAX_NAME];
    uint32_t size;
    uint32_t start_sector;
    uint8_t  attributes;
    uint32_t create_time;
    uint32_t modify_time;
} fs_entry_t;

#define M1FS_MAGIC       0x4D314653  // "M1FS"
#define M1FS_VERSION     0x0100
#define M1FS_BLOCK_SIZE  2048

struct m1fs_superblock {
    uint32_t magic;
    uint16_t version;
    uint16_t block_size;
    uint32_t total_blocks;
    uint32_t free_blocks;
    uint32_t root_block;
    uint8_t  label[16];
    uint8_t  reserved[32];
} __attribute__((packed));

struct m1fs_directory_entry {
    char     name[FS_MAX_NAME];
    uint32_t first_block;
    uint32_t size;
    uint8_t  type;
    uint8_t  attributes;
    uint32_t create_time;
    uint32_t modify_time;
    uint8_t  reserved[16];
} __attribute__((packed));

typedef struct {
    fs_entry_t entry;
    uint32_t position;
    uint8_t  mode;
    uint8_t  dirty;
    uint8_t* buffer;
} file_handle_t;

static file_handle_t open_files[FS_MAX_OPEN];

int fs_open(const char* path, uint8_t mode) {
    int handle = -1;
    fs_entry_t entry;
    
    // Find free handle
    for(int i = 0; i < FS_MAX_OPEN; i++) {
        if(!open_files[i].buffer) {
            handle = i;
            break;
        }
    }
    
    if(handle < 0) {
        return -1; // No free handles
    }
    
    // Look up file entry
    if(fs_lookup(path, &entry) != 0) {
        return -2; // File not found
    }
    
    // Initialize handle
    open_files[handle].entry = entry;
    open_files[handle].position = 0;
    open_files[handle].mode = mode;
    open_files[handle].dirty = 0;
    open_files[handle].buffer = malloc(FS_SECTOR_SIZE);
    
    return handle;
}

#define CONFIG_MAGIC    0x4D314346  // "M1CF"
#define MAX_CONFIG_SIZE 4096
#define MAX_KEY_LENGTH  32
#define MAX_VAL_LENGTH  128

typedef struct config_entry {
    char key[MAX_KEY_LENGTH];
    char value[MAX_VAL_LENGTH];
    struct config_entry* next;
} config_entry_t;

typedef struct {
    uint32_t magic;
    uint16_t version;
    uint16_t num_entries;
    uint32_t checksum;
    config_entry_t* entries;
} config_data_t;

static config_data_t config;

int save_config(void) {
    uint8_t buffer[MAX_CONFIG_SIZE];
    uint32_t offset = 0;
    config_entry_t* entry;
    
    // Write header
    memcpy(buffer + offset, &config.magic, sizeof(uint32_t));
    offset += sizeof(uint32_t);
    memcpy(buffer + offset, &config.version, sizeof(uint16_t));
    offset += sizeof(uint16_t);
    memcpy(buffer + offset, &config.num_entries, sizeof(uint16_t));
    offset += sizeof(uint16_t);
    
    // Write entries
    for(entry = config.entries; entry; entry = entry->next) {
        uint8_t key_len = strlen(entry->key);
        uint8_t val_len = strlen(entry->value);
        
        buffer[offset++] = key_len;
        memcpy(buffer + offset, entry->key, key_len);
        offset += key_len;
        
        buffer[offset++] = val_len;
        memcpy(buffer + offset, entry->value, val_len);
        offset += val_len;
    }
    
    // Calculate and write checksum
    config.checksum = calculate_crc32(buffer, offset);
    memcpy(buffer + offset, &config.checksum, sizeof(uint32_t));
    offset += sizeof(uint32_t);
    
    // Write to storage
    return write_config_sector(buffer, offset);
}

const char* config_get(const char* key) {
    config_entry_t* entry;
    
    for(entry = config.entries; entry; entry = entry->next) {
        if(strcmp(entry->key, key) == 0) {
            return entry->value;
        }
    }
    
    return NULL;
}

int config_set(const char* key, const char* value) {
    config_entry_t* entry;
    
    // Look for existing entry
    for(entry = config.entries; entry; entry = entry->next) {
        if(strcmp(entry->key, key) == 0) {
            strncpy(entry->value, value, MAX_VAL_LENGTH - 1);
            entry->value[MAX_VAL_LENGTH - 1] = '\0';
            return 0;
        }
    }
    
    // Create new entry
    entry = malloc(sizeof(config_entry_t));
    if(!entry) {
        return -1;
    }
    
    strncpy(entry->key, key, MAX_KEY_LENGTH - 1);
    entry->key[MAX_KEY_LENGTH - 1] = '\0';
    strncpy(entry->value, value, MAX_VAL_LENGTH - 1);
    entry->value[MAX_VAL_LENGTH - 1] = '\0';
    
    // Add to list
    entry->next = config.entries;
    config.entries = entry;
    config.num_entries++;
    
    return 0;
}

#define DEBUG_BUFFER_SIZE 1024
#define MAX_BREAKPOINTS 8
#define MAX_WATCHPOINTS 4

typedef enum {
    DEBUG_LEVEL_NONE = 0,
    DEBUG_LEVEL_ERROR,
    DEBUG_LEVEL_WARN,
    DEBUG_LEVEL_INFO,
    DEBUG_LEVEL_DEBUG
} debug_level_t;

typedef struct {
    uint16_t address;
    uint16_t original_opcode;
    bool enabled;
    char description[32];
} breakpoint_t;

typedef struct {
    uint16_t address;
    uint16_t size;
    uint16_t last_value;
    bool enabled;
    void (*callback)(uint16_t addr, uint16_t old_val, uint16_t new_val);
} watchpoint_t;

static struct {
    debug_level_t current_level;
    breakpoint_t breakpoints[MAX_BREAKPOINTS];
    watchpoint_t watchpoints[MAX_WATCHPOINTS];
    char debug_buffer[DEBUG_BUFFER_SIZE];
    uint16_t buffer_pos;
    bool single_step_mode;
} debug_context;

void debug_init(void) {
    debug_context.current_level = DEBUG_LEVEL_INFO;
    debug_context.buffer_pos = 0;
    debug_context.single_step_mode = false;
    
    // Install debug trap handler
    install_trap_handler(debug_trap_handler);
}

int set_breakpoint(uint16_t addr, const char* desc) {
    for (int i = 0; i < MAX_BREAKPOINTS; i++) {
        if (!debug_context.breakpoints[i].enabled) {
            debug_context.breakpoints[i].address = addr;
            debug_context.breakpoints[i].original_opcode = read_memory(addr);
            debug_context.breakpoints[i].enabled = true;
            strncpy(debug_context.breakpoints[i].description, desc, 31);
            
            // Replace instruction with trap
            write_memory(addr, 0xFFFF);  // TRAP instruction
            return i;
        }
    }
    return -1;  // No free breakpoints
}