Introduces ROMs Using Block RAM Resources in VHDL using a template from the Xilinx XST User Guide UG687.

The complete demo project can be found in the VHDL Demos repo.

Setup

In a new Vivado project, the top file should have external ports for clk, reset, sw, and led.

rams_21c is added/copied to the project from Xilinx XST Examples.

The rams_21c instance is instantiated and signals are defined for the 6-bit addr input vector and the 20-bit data output vector. The address vector is input to the ROM from switches [0:6]. The data in the ROM array, although 20-bits wide, has the upper 4 bits set to 0, and the output data will use the lower 16-bits to drive the 16 LEDs on the Basys3 board.

entity rams_top is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           sw : in STD_LOGIC_VECTOR (15 downto 0);
           led : out STD_LOGIC_VECTOR (15 downto 0));
end rams_top;

architecture Behavioral of rams_top is
    signal ram_addr : std_logic_vector(5 downto 0);
    signal ram_data : std_logic_vector(19 downto 0);
begin
    ram_addr <= sw(5 downto 0);

    u_rom : entity work.rams_21c
    port map (
        clk => clk,
        en => '1',
        addr => ram_addr, -- in std_logic_vector(5 downto 0);
        data => ram_data -- out std_logic_vector(19 downto 0));
    );
    led <= ram_data(15 downto 0);
end Behavioral;

Note that in the architecture definition of rams_21c, the rom_type is defined as a descending order array (63 downto 0), so address "000000" should be expected to output 0x0400D.

architecture syn of rams_21c is
    type rom_type is array (63 downto 0) of std_logic_vector (19 downto 0);                 
    signal ROM : rom_type:= (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
                             X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
.
.
.
                             X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
                             X"0030D", X"02341", X"08201", X"0400D"); --<<<<<<<<<<<<<<<<<< address "000000"

    signal raddr : std_logic_vector(5 downto 0);
begin
    process (clk)
    begin
        if (clk'event and clk = '1') then
            if (en = '1') then
                raddr <= addr;
            end if;
        end if;
    end process;
    data <= ROM(conv_integer(raddr));
end syn;

Tool Warnings

A novice attempt to explain and correct some Vivado warnings.

place_design is not in timing mode

Run Implementation emits a warning from the Vivado synthesis tool:

[Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer

The warning is a result of the data signal being connected directly to led.

In the following code, the warning is eliminated by moving the led connection into a process synchronized to rising edge of clk,

begin
    ram_addr <= sw(5 downto 0);
    u_rom : entity work.rams_21c
    port map (
        clk => clk,
        en => '1',
        addr => ram_addr,
        data => ram_data
    );

    out_proc : process(clk)
    begin
        if rising_edge(clk) then
            led <= ram_data(15 downto 0);
        end if;
    end process out_proc;

end Behavioral;

TIMING input delay is missing, output delay is missing

These warnings may not be noticed unless you happen to run the Design Rule Checks. Under the SYNTHESIS section of the Flow Navigator, select Run Synthesis and Report Methodology.

It may be safe to ignore these warnings, they have to do with the fact that Vivado doesn't have enough information to determine the timing impact of connections from the external I/O pins on the board to the FPGA. The warnings can be suppressed with directives in the constraints file telling Vivado to ignore these "false paths" and omit those verbose warnings from the message log.

There's a comment here and hopefully update these wiki pages with some additional information.

If you know the correct syntax, the directives can be added directly to the constraints file:

set_false_path -from [get_ports *sw*] -to [get_clocks sys_clk_pin]
set_false_path -from [get_clocks sys_clk_pin] -to [get_ports *led*]

The Set False Path wizard tool in the Vivado IDE is available to help generate the false_path directives. Under the SYNTHESIS section of the Flow Navigator, select Open Synthesized Design and Edit Timing Constraints.

In the Set False Path dialog shown below, the sw input port is searched in endpoints of type I/O port and the Set button populates the Command string with the get_ports directive.

In a similar fashion sys_clk_pin is appended to the command string as the End Point of the false path.

The false path for the led output ports is specified as From sys_clk_pin and To led*.

The newly generated false path directives must be added to the constraints configuration of the project. When the synthesized design is closed, Vivado will show the Save Constraints prompt where Basys-3-Master.xdc can be selected for update.

Reopen Synthesis and Rerun Report Methodology, there should be “No Violations Found”.

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