Creating a New VHDL Project in Vivado

Launch Vivado and create a new Vivado project for the Basys 3 board

• Select Create Project under Quick Start menu on Vivado welcome page
• Project Name Assign Project name and Project location
• Project Type Be sure RTL Project is selected

Click the Create File button to add a new source file to the project

• Be sure Target language and File type is VHDL
• File name: the top-level entity is often named your-project-name_top.vhd

Add Constraints file for the Basys 3 board

• download constraints files for Digilent boards from their GitHub repo
• click Add Files and browse to select Basys-3-Master.xdc
• “Copy constraints files into project” should usually be checked

Assign Basys3 board file to project

• Be sure Digilent board files have been copied to Vivado/2020.2/data/boards/board_files/
• in the Default Part dialog select the Boards tab and then select Basys3

Define Module

• Default Entity name is the name already given to the VHDL top file under Project Name
• The Architecture name can be modified as desired, or left as the default Behavioral
• Enter I/O Port Definitions

Port Name	Direction	Bus	MSB	LSB
clk	in
reset	in
sw	in	Checked	15	0
led	out	Checked	15	0

Note about case of port names: VHDL is not case sensitive. However, it seems that the Port Names must match the case of the pin labels given in the constraints (.xdc) file.

Inside the project open top.vhd

The entity should have the following port definition:

ENTITY top IS
	PORT (
		clk : IN STD_LOGIC;
		sw : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		led : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END top;

In the architecture block below, the LEDs are connected directly to the switches, allowing the switch states to update continuously.

architecture whatever of rtl_proj_top is

begin

    led <= sw; -- LEDs connected directly to switches

end whatever;

In order to implement the design and program it to the FPGA, it will be necessary to finish setting up the constraints file for the Basys3 board:

• inside the project open Basys3-Master.xdc
• uncomment the lines under Clock signal, Switches, LEDs (lines in the .xdc file are commented with # character)
• Tip: highlight a series of lines, right-click and select "Toggle Line Comments" (or Ctrl+'/')

# Clock signal
set_property -dict { PACKAGE_PIN W5   IOSTANDARD LVCMOS33 } [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

# Switches
set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports {sw[0]}]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports {sw[1]}]
.
.
set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports {sw[15]}]

# LEDs
set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports {led[0]}]
set_property -dict { PACKAGE_PIN E19   IOSTANDARD LVCMOS33 } [get_ports {led[1]}]
.
.
set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports {led[15]}]

To program the FPGA:

• under PROGRAM AND DEBUG, run Generate Bitstream
• select Open Hardware Manager
• select Open Target
• select Program Device

Additional notes on working with the hardware within a Virtual Box environment:

• select the USB device under Virtual Box USB device menu after connecting Basys3 to USB port
• Vivado Hardware Manager errors may be avoided by closing HM after each programming session
• avoid switching out of the VM and then back to the Host, as HM may not be able to connect to target again other than rebooting the VM

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