VHDL Demos

VHDL demonstration projects for the Digilent Basys 3 Artix-7 Fpga Trainer Board.

The Basys 3 is an entry-level development board built around a Xilinx Artix-7 FPGA. The Artix-7 remains in production and as stated on the AMD (formerly Xilinx) website, support is formally being extended for all 7 series devices until at least 2035.

The built-in peripherals integrated onto the Basys 3 board include LEDs, switches, buttons, host USB, seven-segment display, and VGA.

For forgotten reasons, these project were developed in Vivado 2020.2 HLx Edition (as opposed to one of the newer versions).

The VHDL Demos Readme includes more extensive setup instructions for Vivado.

Board Configuration

Please refer to the Basys 3 user manual to ensure that the board is installed and configured properly.

Connecting the board and powering it from the USB port on the development PC, and JTAG programming can be done using the hardware server in Vivado is the most straightforward configuration.

• JP2 set for USB power
• micro-USB cable plugs into J4 PROG port - power is indicated by LD20
• board is powered and and the Artix-7 FPGA is programmed through USB connection from PC to J4
• the FPGA configuration data (bitstream) is sent to the Artix-7e by JTAG and stored in SRAM-based memory cells within the FPGA
• You can perform JTAG programming any time after the Basys 3 has been powered on regardless of what the mode jumper (JP1) is set to
• LD19 DONE is solid green when the board is programmed
• With Programming Mode jumper JP1 set for QSPI, pushing PROG button reloads FPGA with programming stored in SPI flash (the Basys 3 board demo as shipped)

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