Page Index - oRKLLM/ork-driver GitHub Wiki

263 page(s) in this GitHub Wiki:

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• Benchmark Configs Registry
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• Benchmark Standards and Methodology
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• Board Provisioning Rock 5B Plus
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• Building the Regcmd Graph
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• CPU Big Core Contention
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• Exp 2026 06 12 Int4 W4A4
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• Exp 2026 06 12 Int8 W8A8
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• Exp 2026 06 12 Submit Floor Profiling
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• Exp 2026 06 12 Weight Caching
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• Exp 2026 06 13 Activation Quant Reuse
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• Exp 2026 06 13 CPU Affinity Pinning
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• Exp 2026 06 13 FullK Prefill
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• Exp 2026 06 13 Hadamard Int4 Accuracy
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• Exp 2026 06 13 Hybrid M Gate
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• Exp 2026 06 13 Int4 PerChannel Submit
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• Exp 2026 06 13 Matmul Apples to Apples RKNN
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• Exp 2026 06 13 Open vs Closed
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• Exp 2026 06 13 Perf Per Watt
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• Exp 2026 06 13 QKV GateUp Fusion
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• Exp 2026 06 13 Quant SIMD Threading
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• Exp 2026 06 13 Run Multicore Profiling
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• Exp 2026 06 13 Task Batching
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• Exp 2026 06 13 Thread Count Big Cores
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• Exp 2026 06 19 Discovery of INT4 Multi M
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• Exp 2026 06 20 INT4 Stability and Multicore Refactoring
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• Exp 2026 06 21 CPU NEON SIMD Optimizations
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• Exp 2026 06 21 Exhaustive Register Fuzzing and Quantization Mapping
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• Exp 2026 06 21 Mixture of Experts PC Chaining and Scheduler Programming
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• Exp 2026 06 21 Output Zero Copy and Strided Tiling
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• Exp 2026 06 22 INT4 Scheduler Emulation and INT8 State Leakage
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• Exp 2026 06 23 Chaining Resolution
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• Exp 2026 06 23 Decode Profiling
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• Exp 2026 06 23 Hardware Chaining Debug
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• Exp 2026 06 23 Hardware Chaining Zero Overhead
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• Exp 2026 06 23 MoE Expert Offload
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• Exp 2026 06 24 End to End RKLLM Trace Capture and Zero Overhead wait chaining
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• Exp 2026 06 24 PPU LUT Silicon Verification
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• Exp 2026 06 24 RKLLM Multicore Capture
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• Exp 2026 06 25 Layer Streaming and Persist
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• Exp 2026 06 26 DMA Buf Fill Bandwidth
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• Exp 2026 06 26 MoE Decode Partition and Submit Floor
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• Exp 2026 06 26 MoE Expert NPU Viability
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• Exp 2026 06 26 MoE Expert Persist and IOVA Wall
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• Exp 2026 06 26 MoE Routing Skew
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• Exp 2026 06 26 NF4 Imatrix Mixed Precision
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• Exp 2026 06 27 Prefetch Overlap and Stream Pool
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• Exp 2026 06 27 Zero Copy Weight Import
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• Exp 2026 06 28 Multi Domain Residence
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• Exp 2026 06 28 Tiling Autotuner
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• Exp 2026 06 29 Prefill Parity Grind
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• Exp 2026 06 30 Decode Multicore and the Sync Wall
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• Exp 2026 06 30 Prefill NPU Utilization and the Sync Wall
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• Exp 2026 06 30 Weight DMA Amortization
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• Exp 2026 07 01 Multi Domain Residence
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• Exp 2026 07 04 PPU Elementwise Activation Ops
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• Exp 2026 07 05 fp16 Fused SiLU Calibration
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• Exp 2026 07 05 Int8 SiLU Output Quant
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• Exp 2026 07 07 INT4 Multi M Schedule RE
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• Exp 2026 07 08 INT4 BChain Batch Chain
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• Exp 2026 07 10 Forward Softmax and RKNPU Chaining
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• Exp 2026 07 10 Fused Output Activation No Crossing Chain
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• Exp 2026 07 10 On NPU Attention Batched GEMM and Norm
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• Exp 2026 07 12 Matmul Shape Boundaries
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• Exp 2026 07 12 NPU Mode Transition Task Descriptor
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• Exp 2026 07 13 Linear Attention Scans on NPU
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• Exp 2026 07 14 Attention Perchan Scale and CNA Strided Read
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• Exp 2026 07 14 Chained 2 Input SDP ERDMA
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• Exp 2026 07 14 Mode Transition Layer
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• Exp 2026 07 15 NPU Hard Wedge Circumstances
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• Exp 2026 07 16 Dynamic Submit API and Doorbell
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• Exp 2026 07 26 CPU NPU FFN Overlap
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• Exp 2026 07 27 K Slice Size Sweep and the Sched Optimum
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• Exp 2026 07 28 7B Prefill Parity
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• Exp 2026 07 28 M Fold Schedule and CBUF Bank Capacity
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• Exp 2026 08 05 fp16 Colsplit CONTIG
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• Exp 2026 08 17 BigLittle CPU Dispatcher
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• Exp 2026 08 18 GPTQ Int4
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• Exp 2026 08 18 Int4 Expert Coalesce
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• Exp 2026 08 18 Int4 MoE AB Knobs
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• Exp 2026 08 18 NF4 CPU Prefill
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• Exp 2026 08 20 fp16 M Envelope and the CBUF Bank Split
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• Exp 2026 08 20 SDP and Int4 Envelopes
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• Exp 2026 08 21 Native W4A4 Prefill Hang
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• Exp 2026 08 22 mode_probe Kernel Oops
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• Exp 2026 08 22 W4A4 Reference Model
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• Exp 2026 08 23 W4A4 PPL Journey
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• Exp 2026 09 03 KV Cache Quantization
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• Exp 2026 09 05 Fixed Per Task Cost
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• Exp 2026 09 05 Heterogeneous Dispatch Ceiling
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• Exp 2026 09 05 Session Findings
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• Exp 2026 09 05 SRAM Aggregate Bandwidth
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• Exp 2026 10 07 W4A4 vs GGUF 4bit Baseline
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• Exp 2026 10 08 fp16 Wide K Head Hang
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• Exp 2026 10 09 Colsplit Whole Buffer Cache Maintenance
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• Exp 2026 10 09 fp16 K Slice and the Training Step
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• Exp 2026 10 09 fp16 K Slice Is Inert On The Inference Path
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• Exp 2026 10 09 PR390 Alone Does Not Fix The Domain Switch
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• Exp 2026 10 09 The Domain Reference Leak
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• Exp 2026 10 11 Weight Ownership Under Mmap
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• Exp 2026 10 12 fp16 M Envelope Is A Predicate
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• Exp 2026 10 12 INT4 BCHAIN Dispatch Envelope
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• Exp 2026 10 12 Shared Doorbell Drain Defects
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• Exp 2026 10 12 W4A4 Tier Trade
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• Exp 2026 10 13 INT4 BCHAIN Completion Gate
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• Experiment Log
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• Feasibility Log
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• Fuzzing and Dynamic Tracing
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• Heterogeneous Serving and Scheduling
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• Hybrid Precision Decode Architecture
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• INT4 BCHAIN Operational Notes
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• K Grouping Cost On RK3588
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• Kernel Modifications
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• Model Recipes
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• NPU on chip SRAM
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• NPU Op Notes Recovered From npu.c
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• NPU Quirks
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• Optimization Roadmap
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• PC chaining and the M tile schedule
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• Performance
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• Precision Capability Matrix
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• Prior Art on Model and Register Fuzzing
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• Quantization Paths and Baselines
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• README
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• Recording Investigation Notes
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• regcmd ISA Reference
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• Reverse Engineering Roadmap
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• Roadmap Edge Asymmetric SLM
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• Robustness and Defensive Guards
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• Vendor Kernel Behaviour
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