Experiment 7: Linear Feedback Shift Register (LFSR) and PRBS - ml7715/VERI-Laboratory GitHub Wiki

This experiment requires us to implement a 7-bit LFSR using the polynomial 1+X+X^7.

An example of LFSR implementing the polynomial 1+X^3+X^4 is the following:

In order to implement the polynomial 1+X+X^7 on the other hand the 7th and 1st output of a 7-bit shift-register are fed to a xor gate and then to the input of the shift-register itself.

Before implementing the circuit in verilog the values produced by the LFSR were calculated manually. The outputs obtained when the shift register is initialized to 7'b1 are: 1, 3, 7, 1F, 3F, 7F, 7E, 7D, 7A, 75.

The LFSR was then implemented in verilog as follows:

module LFSR(CLK, COUNT);
	input CLK;
	output[7:1] COUNT;
	reg[7:1] COUNT;
	initial COUNT = 7'd1;
		
	always @ (posedge CLK)
		COUNT <= {COUNT[6:1], COUNT[7] ^ COUNT[1]};
		
endmodule

As we can see a 7-bit shift register was created and its input was set to COUNT[7] ^ COUNT[1] in order to implement the primitive polynomial wanted.

A top module was then generated to link all the parts of the circuit together, KEY[3] was used to drive the clock of the LFSR. Therefore a new value is generated each time the key is pressed.

top module in verilog:

module ex7(KEY3, HEX0, HEX1);

	input KEY3;
	output [6:0] HEX0, HEX1;

	wire [7:0] count;
	
	LFSR(KEY3, count);
	
	hex_to_7seg h0(HEX0, count[3:0]);
	hex_to_7seg h1(HEX1, count[7:4]);

endmodule

The design was then compiled and sent to the FPGA. The values generated correspond to the ones calculated manually.