Page Index - enjoy-digital/litex GitHub Wiki
100 page(s) in this GitHub Wiki:
- Home
- Welcome to LiteX!
- Typical LiteX design flow:
- Examples of designs built with LiteX:
- Sponsors/Partners:
- Papers, Presentations, Tutorials, Links
- Sub-packages
- Quick start guide
- Community
- Contact
- Add A New Board
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- Add A New Core
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- Add A New CPU
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- AXI Bus
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- Cores
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- Cores Ecosystem
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- CPUs
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- Create A complex SoC With Cores From The Ecosystem
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- Create A minimal SoC
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- Create A PCIe SoC
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- Create And Load Software To The CPU
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- CSR Bus
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- Document a SoC
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- Export Your Core SoC To Verilog
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- Feedback Contribution Support
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- Firmware
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- FPGA and SPI Flash programmers
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- Generate Renode simulation
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- Hard core CPUs
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- Host Bridges
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- Installation
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- JTAG GDB Debugging with VexRiscv CPU
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- JTAG GDB Debugging with VexRiscv SMP NaxRiscv VexiiRiscv CPUs
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- LiteX for Hardware Engineers
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- Load Application Code To CPU
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- Migen Amaranth
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- OS support
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- OSes Ecosystem
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- Projects
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- Related Projects
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- Reuse a (System)Verilog, VHDL, Amaranth, Spinal HDL, Chisel core
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- Run Linux On Your SoC
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- Run MicroPython CircuitPython On Your SoC
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- Run Zephyr On Your SoC
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- SoC builder
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- SoC Documentation
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- SoC Simulator
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- Soft CPU
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- Streams
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- Tutorials Resources
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- Use Host Bridge to control debug a SoC
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- Use LiteScope To Debug A SoC
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- Use LiteX on the Acorn CLE 215
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- Use‐GDB‐with‐VexRiscv‐SMP‐NaxRiscv‐VexiiRiscv CPUs
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- Wishbone Bus
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