Tutorial 4: Wideband Pocket Correlator

Author: W.New (Version 1). Irappa M. Halagali , Sandeep C. Chaudhari , Mekhala V. Muley , Shelton Gnanaraj J. (Version 2)

Expected completion time: 2 hours

In this tutorial, you will create a simple Simulink design which uses the iADC board on ROACH and the CASPER DSP blockset to process a wideband signal, channelize it and output the visibilities through ROACH's PowerPC.

By this stage, it is expected that you are familiar with the tutorials Introduction to Simulink, Implementation of a Green Block, 10GbE Interface and are reasonably comfortable with Simulink and basic Python. We will focus here on higher-level design concepts, and will provide you with low-level detail pre-implemented.

Some of this design is similar to that of Wideband_Spectrometer tutorial, so completion of it is recommended.

When doing correlation on a set of antennae we introduce the term baseline. A baseline is the product of the signal from two antennas. We calculate all baselines. For example, if we have 3 antennae, A, B and C, we need to perform correlation across each baseline, AB, AC and BC. We also need to do auto-correlations, which will give us the power in each signal. ie AA, BB, CC. We will see this implemented later.

Dish type receivers are typically dual polarized (horizontal and vertical feeds). Each polarization is fed into separate ADC inputs. When correlating these antennae, we differentiate between full Stokes correlation or a half Stokes method. A full Stokes correlator does cross correlation between the different polarizations (i.e. for a given two antennas, A and B, it multiplies the horizontal feed from A with the vertical feed from B and vice-versa). A half stokes correlator only correlates like polarizations with each other, thereby halving the compute requirements.

   Our correlator here is a half Stokes correlator. We will be feeding the similar polarizations of two antennae to the two inputs of the single ADC.

The correlator we will be designing is a 2 antenna single channel correlator i.e it takes the similar polarization from two antenna and correlates the signal, hence we will be populating only one adc board on the ROACH.

Click here for Complete information of Turorial Lab & Setup at Casper Workshop 2011, Pune, India. The lab at the workshop is pre-configured with the CASPER libraries, Matlab and Xilinx tools. If you want to try this tutorial in your lab, please refer the topics : H/W & S/W requirements and SET-UP of Tutorials at WORKSHOP 2011 ,Compiling the Design & Programming on ROACH FPGA and Locations & Files information for the WORKSHOP 2011 wherever applicable in the link Complete information of Turorial Lab & Setup.

Start Matlab and open Simulink (either by typing simulink on the Matlab command line, or by clicking the Simulink icon in the taskbar). Create a new model and add the Xilinx System Generator and XSG core config blocks as before in Introduction to simulink.

By now you should have used these blocks a number of times. Pull the System Generator block into your design from the Xilinx Blockset menu under Basic Elements. The settings can be left on default.

The XSG block can be found under the BEE_XPS System Blockset. Set the Hardware platform to ROACH:sx95t, the Clock Source to adc0_clk and the rest of the configuration as the default.

Make sure you have an ADC plugged into ZDOK0 to supply the FPGA's clock!

Set the XSG core config block as shown below

The Sync Generator puts out a sync pulse which is used to synchronize the blocks in the design. See the CASPER memo on sync pulse generation for a detailed explanation and the iBOB iADC tutorial for an example on its basic use.

Whenever a sys_rst is given through the software register a mrst signal is generated which resets the entire MAC block. Sync pulse is generated with a period of 2^27 clock cycles and resets all the blocks.

Connection of the ADC is as in Wideband Spectrometer tutorial except for the sync outputs.

Set up the ADC as shown below

For the purposes of simulation (and to satisfy Simulink's requirements that all inputs be connected), we need to put input signals into the ADCs. These blocks are pulse generators in the case of sync inputs and any analogue source for the RF inputs (noise, CW tones etc).

The set up for these blocks is as shown below

This part of the Simulink design sets up a software register which can be configured through the controlling software from the PC to control the correlator. Set the yellow software register's IO direction as from processor. You can find it in the BEE_XPS System blockset. The constant block input to this register is used only for simulation.

There are several such software registers in the design, a couple of those are shown in the above figure.

The coarse delay block can be found under Casper DSP Blockset → Delays. The delay block is used to delay the simultaneous data stream by specified number of clock cycles.

Configure the delay blocks as shown below

The PFB FIR and FFT are the heart of this design. The PFB and the FFT are connected as shown below

Configure the PFB_FIR_real blocks as shown below

Downshifting block

   There is potential to overflow the first FFT stage if the input is periodic or signal levels are high as shifting inside the FFT is only performed after each butterfly stage calculation. For this reason, we  recommend casting any inputs up to 18 bits with the binary point at position 17 (thus keeping the range of values -1 to 1), and then downshifting by 1 bit to place the signal in one less than the most significant bits.

The downshifing block is a static block and hence is not present in the casper library. The block has to be copied from the “[TUT4_MDL_DOWNSHIFT_FILE]” mdl file present in the location “[STD_MDL_DIR]”.

The fft_wide_band_real block should be configured as follows

The fine delay block is parameterised as shown below

The equaliser block is set to 512 FFT channels and the Subsystem is designed as seen below. The equiliser reduces the bit growth that was introduced in the PFB and FFT. We can do this because we do not need the full dynamic range.

The block is a static block and hence is not present in the casper library. The block has to be copied from the “[TUT4_MDL_EQ_FILE]” mdl file present in the location “[STD_MDL_DIR]”.

The following sections are more periphery to the design and will only be touched on. By now you should be comfortable putting the blocks together and be able to figure out many of the values and parameters.

As a kind of debug output we can wire up the LEDs to certain signals. We light an LED with every sync pulse. This is a sort of heartbeat showing that the design is clocking and the FPGA is running.

The led “led_new_acc” gives a visual indication of when an accumulation is complete while the “led_overflow” led indicates any clipping encountered in ADC, FFT or Qunatiser stages.

Since the signals might be too short to light up an LED and for us to actually see it (consider the case where a single ADC sample overflows; 1/800MHz is 1.25nS – much too short for the human eye to see) we add a negedge delay block which delays the negative edge of a block, thereby extending the positive pulse. A length of 2^23 gives about a 10ms pulse.

The multiply and accumulate is performed in the dir_x (direct-x) blocks, so named because baselines are calculated directly, in parallel (as opposed to the packetised correlators' X engines which process serially).

Accumulation for each baseline takes place in BRAM using the same simple vector accumulator used in the Wideband spectrometer tutorial.

The MAC block is a static block and hence is not present in the casper library. The block has to be copied from the “[TUT4_MDL_MAC_FILE]” mdl file present in the location “[STD_MDL_DIR]”.

CONTROL:

Sys_rst software register is for resetting the complete design. Sync LED provides a “heartbeat” signal to instantly see if your design is clocked sensibly. Similarly the coarse delay, fractional delay and fringe stop values can be provided runtime via script. New accumulation LED gives a visual indication of data rates and dump times. Also the Overflow LED is the indication of data overflow at any stage in the design flow.

By giving bee_xps command in the matlab window we will get a pop-up. Make sure the file displayed in the pop-up is correct and then press RUN to start the compilation. After compilation, it creates a directory named after the model file name without the .mdl extension. There is a sub directory named bit_files. In this bit_files directory there are .bit and .bof file. We need the .bof file to program the FPGA.

You need to copy this .bof file at location [FPGA_PROG_BOF_DIR] after changing the permissions of the file.

eg. for the bof file [TUT4_BOF_FILE] in the area [STD_BOF_DIR]

$ chmod a+x [STD_BOF_DIR]/[TUT4_BOF_FILE]

$ cp [STD_BOF_DIR]/[TUT4_BOF_FILE] [FPGA_PROG_BOF_DIR]

The python scripts are located in the “[STD_PYSCRIPT_DIR]” directory. We first need to run “[TUT4_CONFIG_PYSCRIPT_FILE]” to program the FPGA and configure the design. Then we can run the script “[TUT4_PLOT_PYSCRIPT_FILE]” to plot the self, cross and the phase.

Usage:[STD_PYSCRIPT_DIR]/[TUT4_CONFIG_PYSCRIPT_FILE] <ROACH name/IP> -b

eg. $[STD_PYSCRIPT_DIR]/[TUT4_CONFIG_PYSCRIPT_FILE] roach030172 -b [TUT4_BOF_FILE]

            Enter the corresponding Location/File names and roach name/IP.    

Note : Enter your roach number! You will see on display.

$[STD_PYSCRIPT_DIR]/[TUT4_PLOT_PYSCRIPT_FILE] <ROACH name/IP> -l

            Enter the corresponding Location/File names and roach name/IP.

This script grabs auto-correlations, cross-correlation and the phase from the brams and plots them. The following plot gives the self spectrum, cross correlation and the phase between the two input signals.

Pocket correlator tutorial completed. We have observed the auto-correlations AA & BB for the two inputs we have fed to iADC and we have also observed the cross power and phase spectrum.