LOCATIONSandFILES - david-macmahon/wiki_convert_test GitHub Wiki
Tutorial Lab, Instructions, H/W & S/W Requirements and Locations & Files - CASPER-2011
Tutorial lab at WORKSHOP 2011 is having 14 workstations named gmrt1 to gmrt10 for FPGA tutorials , gmrt11 to gmrt14 for NVidia demo and gpunode3 & gpunode4 for GPU tutorials. Each FPGA workstaion is having seperate ROACH unit (SKA group brought 4 numbers and 7 were spared from GMRT project) with ether net connection from the local PC. By default ROACH units are getting booted in netboot with ip assigned by the local PC. All instructions related to TUTORIALS are made available on wiki page , Desktop of all workstations and printouts displayed at 2 locations in the lab. To issue licences to all these workstations 3 servers are used. One for Xilinx and two for MATLAB. One server m/c with 5 licences of 2008a purchased by GMRT/NCRA/TIFR and another server m/c with 5 licences of 2011a trial version sponsored by MATLAB with 21 days validity. Two HARD DISKs are mounted , one each on MATLAB server m/c's. These HARD DISKs are getting mounted automatically on all workstations after bootup. One for putting all the standard MODEL, BOF, PYTHON SCRIPTS and DOCUMENT files with only read permission. Also to save the designs created by users. Another HARD DISK for taking the backup of the user designs at 10pm everyday.
Live demo of GMRT signals also arranged for half an hour on two days of the workshop. This is arranged to give the feel of astronomical signals and an idea about the GMRT instrument.
This LAB setup is done by DIGITAL BACKEND group under the guidance of Prof. Yashwant Gupta and Mr. Ajit Kumar B. and the support extended by COMPUTER and ELECTRICAL groups. Digital Group members : Mr. Sandeep C. Chaudhari , Ms Mekhala V. Muley , Mr. Gnanaraj Shelton J. , Mr. Kaushal D. Buch , Mr. Harshavardhan Reddy S., Mr. Irappa M. Halagali and Mr. Indukumar S. Bhonde.
= '''Instructions to start Tutorials at WORKSHOP 2011 ''' =
- {|
| gmrt1 ... gmrt10 || (FPGA tutorials) || : user, || : user123 |- | gmrt11 ... gmrt14 || (NVidia tutorials) || : user, || : user123 |- | gpunode3, gpunode4 || (GPU tutorials) || : gmrt, || : casper2011 |- |}
On first login, create user_directory to save all your tutorial related work.
- cd /casper/trial mkdir
This will create a separate user_directory ( /casper/trial/ ) where you can save all your files related to tutorials, like model files, python scripts, bof files or any other files which you may need to run the tutorials. This area will be visible on all machines in the tutorial lab, so you can easily continue your work next day.
To start Matlab in the user machine do the following,
: cd /data/matlab [enter]
: ./startsg_new.sh [enter]
Matlab will now open. Now simulink can be opened by either typing simulink on the Matlab command line, or by clicking the Simulink icon in the Matlab taskbar.
| [STD_MDL_DIR] | : /casper/workshop/MDL_files/ |
| [STD_BOF_DIR] | : /casper/workshop/BOF_files/ |
| [STD_PYSCRIPT_DIR] | : /casper/workshop/PY_SCRIPTS/ |
| [DOC_DIR] | : /casper/workshop/SOPs_DOC/ |
SET-UP of Tutorials at WORKSHOP 2011
The Hardware and Software used/required for this tutorial : {| width="500" border="1" cellpadding="3" |+HARDWARE ! Hardware ! Description |- | PC | Dell Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz width 64 bit & 4GB RAM |- | ROACH unit | version 1.0 Rev 3 2009, uboot :
| uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110. |
|---|
| } |
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
SOFTWARE
SET-UP : The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file “LOCATIONSandFILES.pdf” in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different ! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs are already done.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file , eth1 should be configured. And in the file /etc/hosts , ip address and corresponding roach board (host) name entry to be done.
3. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT1_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT1_BOF_FILE]” to directly program (using the python script explained in “Software”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT1_MDL_FILE]”.
4. Start the matlab :
$ cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$ ./[MATLAB_START_FILE] &
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | Dell Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz width 64 bit & 4GB RAM |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110 |
| 10Gbe Myricom card | Installed in the PC with drivers. |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
| Wireshark | Running on Linux 2.6.35-30-generic, with libpcap version 1.1.1, GnuTLS 2.8.6, Gcrypt 1.4.5. |
| TCPdump | tcpdump-4.1.1 |
| GULP | version 2.0, January 2004 |
| iperf | version 2.0.4 (7 Apr 2008) pthreads |
| jperf | version 2.0.2 |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file, eth1 should be configured. And in the file /etc/hosts, ip address and corresponding roach board(host) name entry to be done.
3. a. To test the 10Gbe data Transfer and Receive in the loop back mode : Connect the CX4-10Gbe cable between Port 0 (rightmost bottom if we view the ROACH UNIT from the backside) to the Port 3 (bottom one , adjacent to J25 connector).
b. To test the 10Gbe data Transfer and Receive between ROACH unit and PC :
Connect the CX4-10Gbe cable between Port 0 (rightmost bottom if we view the ROACH UNIT from the backside) to the connector on the 10Gbe Myricom card installed in the PC.
4. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT2_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT2_BOF_FILE]” to directly program (using the python script explained in “Software”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT2_MDL_FILE]”.
5. Start the matlab :
$ cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$ ./[MATLAB_START_FILE] &
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | Dell Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz width 64 bit & 4GB RAM |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110, iADC : BEE2 DUAL 1 GHz ADC BOARD version 1.1 |
| Signal generator | Signal generator to feed clock of 800MHz, 0dbm to ROACH unit through iADC's clk_i input. |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file, eth1 should be configured. And in the file /etc/hosts, ip address and corresponding roach board(host) name entry to be done.
3. Feed the clock of 800MHz , 0 dbm to the clk_i input of the iADC card from the Signal generator
4. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT3_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT3_BOF_FILE]” to directly program (using the python script explained in “Software”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT3_MDL_FILE]”.
5. Start the matlab :
$ cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$ ./[MATLAB_START_FILE] &
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | Dell Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz width 64 bit & 4GB RAM |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110, iADC : BEE2 DUAL 1 GHz ADC BOARD version 1.1 |
| Signal generator | Signal generator to feed clock of 600MHz, 0dbm to ROACH unit through iADC's clk_i input. |
| Waveform generator | Input signals from waveform generator should be of -13dbm@400 MHz BW ( Total power over BW ) to the I+ & Q+ inputs of iADC. |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file, eth1 should be configured. And in the file /etc/hosts, ip address and corresponding roach board(host) name entry to be done.
3. Feed the clock of 600MHz, 0 dbm (~630mvPkPk without any splitter) to the clk_i input of the iADC card (which is plugged in the ZDOK 0 connector of the roach board located near to mmc card/power supply) from the signal generator. The python script “[TUT4_CONFIG_PYSCRIPT_FILE]” generates the soft sync and hence there is no need to give a external sync pulse.
4. Connect the input signals to I+ & Q+ of the iADC 0 (in the ZDOK 0 connector of the roach board ) from the noise generator. The signals will be referred as a(adc0I+), b(adc0Q+). The input signals should be of -13dbm(~282mvPkPk with 2 way power splitter )@300 MHz BW ( total power over BW ) at the iADC card input. A low pass filter of 200 Mhz BW is introduced in the signal path to show a band shape. The output will generate two self signals “aa”, “bb” and one cross “ab” for this tutorial. Thus we get 2 auto-correlations and 1 cross-correlation.
5. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT4_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT4_BOF_FILE]” to directly program (using the python script explained in “Software”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT4_MDL_FILE]”.
6. Start the matlab :
$cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$ ./[MATLAB_START_FILE] &
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | GPU PC |
| Nvidia GPU card | Tesla C2050 installed in the GPU PC. |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110, iADC : BEE2 DUAL 1 GHz ADC BOARD version 1.1 |
| Signal generator | Signal generator to feed clock of 800MHz, 0dbm to ROACH unit through iADC's clk_i input. |
| Waveform generator | Input signals from waveform generator should be of -2.5dbm (500mv PkPk)@200 MHz BW ( Total power over BW ) to the I+ input of iADC. |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
| CUDA | release 4.0 , V 0.2.1221 |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file, eth1 should be configured. And in the file /etc/hosts, ip address and corresponding roach board(host) name entry to be done.
3. Feed the clock of 800MHz , 0 dbm to the clk_i input of the ADC card (which is plugged in the ZDOK 0 connector near to mmc card/power supply) from the Signal generator.
4. Connect the input signals to I+ iADC 0 (in the ZDOK 0 connector). The input signal should be of -2.5dbm(500mv PkPk)@200 MHz BW(Total power over BW) at the iADC card input.
5. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT5_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT5_BOF_FILE]” to directly program (using the python script explained in “Software”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT5_MDL_FILE]”.
6. Start the matlab :
$ cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$ ./[MATLAB_START_FILE] &
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | Dell Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz width 64 bit & 4GB RAM |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110 |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file, eth1 should be configured. And in the file /etc/hosts, ip address and corresponding roach board(host) name entry to be done.
3. seed_value.m file must be kept in the directory [MATLAB_START_DIR].
4. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT6_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT6_BOF_FILE]” to directly program (using the python script explained in “Running the design”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT6_MDL_FILE]”.
5. Start the matlab :
$cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$./[MATLAB_START_FILE]
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | Dell Intel(R) Core(TM) i3 CPU 530 @ 2.93GHz width 64 bit & 4GB RAM |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110 |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the Serial port cable between the ROACH board's P2 connector and serial port of the PC (on which minicom program exists).
2. Connect the Ethernet cable to J25 port of the ROACH board from the PCs eth1 port. /etc/ethers file should have mac address and corresponding ip address. In the /etc/network/interfaces file, eth1 should be configured. And in the file /etc/hosts, ip address and corresponding roach board(host) name entry to be done.
3. This tutorial requires just the FPGA board and not the iADC board. The onboard clock of 100MHz will be used for this tutorial.
4. The controlling PC should have following softwares installed in it :
MATLAB (2008a)
ISE 11.5
System Generator 11.5
Latest CASPER library
5. Create your own directory at “[USER_DIR]” , where you can save and compile your model file or save any work that you may do. There are three ways to implement this tutorial.
A)You can either copy the mdl file “[TUT7_MDL_FILE]” from the the area “[STD_MDL_DIR]” to the directory that you have created at “[USER_DIR]” and compile it in the MSSGE (Matlab-Simulink-System Generator) environment
OR
B)You can use the bof file kept in the area “[FPGA_PROG_BOF_DIR]/[TUT7_BOF_FILE]” to directly program (using the python script explained in “Data acquisition”) the FPGA and look at the results
OR
C)Follow the steps given below to create the mdl file similar to the file “[STD_MDL_DIR]/[TUT7_MDL_FILE]”.
6. Start the matlab :
$ cd [MATLAB_START_DIR]
[MATLAB_START_DIR]$ ./[MATLAB_START_FILE] &
The Hardware and software used/required for this tutorial
| Hardware | Description |
|---|---|
| PC | GPU PC |
| ROACH unit | version 1.0 Rev 3 2009, uboot : uboot-2010-07-15-r3231-dram, Linux Kernel Image : uImage-jiffy-20091110, iADC : BEE2 DUAL 1 GHz ADC BOARD version 1.1 |
| Signal generator | Signal generator to feed clock of 400MHz, 0dbm to ROACH unit through iADC's clk_i input. |
| Waveform generator | Input signals from waveform generator should be of -13dbm@400 MHz BW ( Total power over BW ) to the I+ & Q+ inputs of iADC. |
HARDWARE
| Software | Description |
|---|---|
| OS | Linux 2.6.35-30-generic #54-Ubuntu 10.10 SMP x86_64 GNU/Linux |
| Matlab | 2008a |
| Xilinx | ISE version 11.5 |
| CASPER lib | gits_100511 |
| Python | version 2.6 |
| corr package | corr-0.6.5 |
| minicom | version 2.4 ( compiled on Jun 3 2010) |
| Other softwares | PSRDADA and TAX |
SOFTWARE
Setup The lab at the workshop is preconfigured with the CASPER libraries, Matlab and Xilinx tools. For locations/directories and files information required in the tutorial , please refer the topic "Locations & Files information for the WORKSHOP 2011" here or the file LOCATIONSandFILES.pdf in the home/Desktop area or LOCATIONSandFILES slides displayed.
Note1 : The Date and Time portion of the BOF file name will be different! It depends upon when (Date & Time) you complile your model file !
Note2 : All the following cable connections and entries in the /etc/* files of the workshop PCs have already been done. You are not required to do any of the following setup and they are informatory in nature. You can verify points 1 to 4 on the setup you are working on and if you have any doubts regarding them kindly contact the lab instructor. Kindly go through point 5 to decide the way you will implement the tutorial.
1. Connect the ROACH board to the controlling PC using 100MBPS ethernet and RS-232 serial cable.
2. Feed the clock of 400MHZ,0dbm to the clk_i input of the iADC card from the signal generator.
3. Connect the input signals to i and q of the iADC from the noise generator. The input signal should be of -13dbm(with 2 way power splitter)@200MHz bandwidth at the iADC card input.
4. Connect the ROACH board to the CPU_GPU PC using 10gbE cable. Connect one end of 10gbE cable's CX4 connector to the CX-4 port of ROACH and the other end to the 10gbE card on the CPU-GPU PC.
5. Boot the ROACH using mmcboot and copy the [TUT9_BOF_FILE] to the directory [TUT9_FPGA_PROG_BOF_DIR] on controlling PC. Design details of the bof file are not given. But, if Matlab is available, the MDL file can be opened and design can be viewed. The MDL file [TUT9_MDL_FILE] is located at [TUT9_MDL_DIR].
Note`` ``:`` ``Tutorials`` ``8`` ``,`` ``10`` ``&`` ``11`` ``are`` ``of`` ``demo`` ``type`` ``from`` ``Nvidia.
To compile a design go to matlab command window and run the command “bee_xps”. A new window “BEE-XPS 1.1” will pop-up. Leave all options as defaults, do not make any changes. Confirm that the file name given in the “System Generator Design Name” field is correct. If it is not, click anywhere on your design such that it is the highlighted window, then click “gcs”. To start the process, simply click “Run XPS”. Compilation will take some time based on the design and at the end of compilation a new pop-up with “BEE-XPS run successfully completed in hrs:mnim:sec !” will be shown.
After compilation, it creates a sub-directory inside the directory with model file, named as <model_file_name> (without the .mdl extension). Inside this sub-directory a sub-directory named “bit_files” will be created with .bit and .bof files. Of these we need the .bof file to program the FPGA.
eg : First a directory will be created like “/casper/trial//<model_file_name>” : Then a sub-directory “casper/trial//<model_file_name>/bit_files” will be created. : We are interested in the file “/casper/trial//<model_file_name>/bit_files/*.bof”
You need to use the file “/casper/trial//<model_file_name>/bit_files/*.bof” for programming the FPGA on ROACH. Do the following : : Set the permissions : : $ chmod a+x “/casper/trial//<model_file_name>/bit_files/*.bof” : Copy the file : : $ cp /casper/trial//<model_file_name>/bit_files/*.bof /srv/roachboot/etch_devel/boffiles/
To program the FPGA on ROACH , use one of the following way ;
Programming through "ssh" :
- ssh -X root@ cd /boffiles ./<bof_file> # Programs the FPGA
Programming through "telnet" :
- telnet #port number is 7147. ?listbof #should start with ? #lists the boffiles in /srv/roachboot/etch_devel/boffiles/ ?progdev # Programs the FPGA. # To quit the telnet press ctrl + ] key & then quit.
Programming through "minicom" :
- minicom -w # start minicom with line wrap option -w as super user. login : root # w/o password. cd /boffiles ./ # Programs the FPGA
Programming through "Python Script" :
- ./<python_program> -b #Tutorials those have python scripts with this option.
LOCATIONSandFILES.pdf {| |[HOME_DIR] : || /home/user/ |- |[DESKTOP_DIR] : || /home/user/Desktop/ |- |[MATLAB_START_DIR] : || /data/matlab/ |- |[FPGA_PROG_BOF_DIR] : || /srv/roachboot/etch_devel/boffiles/ |- |[STD_MDL_DIR] : || /casper/workshop/MDL_files/ |- |[STD_BOF_DIR] : || /casper/workshop/BOF_files/ |- |[STD_PYSCRIPT_DIR] : || /casper/workshop/PY_SCRIPTS/ |- |[DOC_DIR] : || /casper/workshop/SOPs_DOC/ |- |[USER_DIR] : || /casper/trial/ |- |[GULP_DIR] : || /data/Gulp/ |- |[GPU_PC_DIR] : || /home/gmrt/workshop/ |- |[TUT9_MDL_DIR] : || /home/gmrt/mdl_files |- |[TUT9_FPGA_PROG_BOF_DIR] :|| /opt/ROACH |- |[TUT9_PYTHON_DIR] : || /home/gmrt/python_scripts |- |[TUT9_DELAY_DIR] : || /home/gmrt/delay_cal |- |[TUT9_TAX_DIR] : || /home/gmrt/tax |- |[CASPER_LIB_DIR] : || /data/casper_git/mlib_devel/casper_library/ |- |}
“Note : * The date & time portion of the BOF file name will be different from the file names written below! ”
| [MATLAB_START_FILE] : | startsg_new.sh |
| [TUT1_MDL_FILE] : | tut1_intro_ise.mdl |
| [TUT1_BOF_FILE] : | tut1_intro_ise_2011_Jul_13_1555.bof* |
| [TUT1_DOC_FILE] : | casper_workshop_tut1.pdf |
| [TUT2_MDL_FILE] : | tut2_10gbe.mdl |
| [TUT2_BOF_FILE] : | tut2_10gbe_2011_Jul_05_1639.bof* |
| [TUT2_DOC_FILE] : | casper_workshop_tut2.pdf |
| [TUT2_PYSCRIPT_FILE] : | tut2.py |
| [TUT3_MDL_FILE] : | tut3_r_spec_2048_r105.mdl |
| [TUT3_BOF_FILE] : | tut3_r_spec_2048_r105_2011_Jul_06_1251.bof* |
| [TUT3_DOC_FILE] : | casper_workshop_tut3.pdf |
| [TUT3_PYSCRIPT_FILE] : | tut3_spectrometer.py |
| [TUT4_MDL_FILE] : | tut4_wideband_poco.mdl |
| [TUT4_MDL_DOWNSHIFT_FILE] : | tut4_downshift.mdl |
| [TUT4_MDL_EQ_FILE] : | tut4_eq.mdl |
| [TUT4_MDL_MAC_FILE] : | tut4_mac.mdl |
| [TUT4_BOF_FILE] : | tut4_wideband_poco_2011_Sep_14_1639.bof* |
| [TUT4_DOC_FILE] : | casper_workshop_tut4.pdf |
| [TUT4_CONFIG_PYSCRIPT_FILE] : | tut4_poco_config.py |
| [TUT4_PLOT_PYSCRIPT_FILE] : | tut4_poco_plot.py |
| [TUT5_MDL_FILE] : | tut5_gpu_spec.mdl |
| [TUT5_BOF_FILE] : | tut5_gpu_spec_2011_Jul_06_1707.bof* |
| [TUT5_DOC_FILE] : | casper_workshop_tut5.pdf |
| [TUT5_INIT_PYSCRIPT_FILE] : | tut5_gpu_spec_init.py |
| [TUT5_PLOT_GPU_SPECT_PYSCRIPT_FILE] : | tut5_plot_gpu_spectrum.py |
| [TUT5_GPU_FFT_CEXE_FILE] : | tut5_gpu_fft |
| [TUT5_GPU_FFT_C_FILE] : | tut5_gpu_fft.c |
| [TUT6_MDL_FILE] : | tut6_digital_noise_src.mdl |
| [TUT6_BOF_FILE] : | tut6_digital_noise_src_2011_Sep_23_1128.bof* |
| [TUT6_DOC_FILE] : | casper_workshop_tut6.pdf |
| [TUT6_PYSCRIPT_FILE] : | tut6_run.py |
| [TUT6_MATLAB_FILE] : | seed_value.m |
| [TUT7_MDL_FILE] : | tut7_coarse_delay_blk.mdl |
| [TUT7_BOF_FILE] : | tut7_coarse_delay_blk_2011_Sep_23_1151.bof* |
| [TUT7_DOC_FILE] : | casper_workshop_tut7.pdf |
| [TUT7_PYSCRIPT_FILE] : | tut7_rsnaprun_corr_delay.py |
| [TUT9_MDL_FILE] : | tut9_adc_packet_8192.mdl |
| [TUT9_MDL_PIC] : | tut9_adc_packet_8192.png |
| [TUT9_BOF_FILE] : | tut9_adc_packet_8192_2011_Oct_01_0014.bof |
| [TUT9_DOC_FILE] : | casper_workshop_tut9.pdf |
| [TUT9_USER] : | gmrt |
| [TUT9_GPU_PC] : | gpunode4 or gpunode3 |
| [TUT9_CTRL_PC] : | gpunode4 |
| [TUT9_CTRL_PC_IP] : | 192.168.50.24 |
| [TUT9_CTRL_PC_PASS] : | casper2011 |
| [TUT9_TENGB_IP] : | 192.168.8.201 for gpunode4 and 192.168.8.202 for gpunode3 |
| [TUT9_TENGB_PORT] : | 10000 |
| [TUT9_CONFIG_PY] : | init_1.py for gpunode3 and init_2.py for gpunode4 |
| [TUT9_RAW_DATA_FILES] : | channel1_400MB.raw,channel2_400MB.raw |
| [ROACH_BOOT_PROC_FILE] : | Roach_BOOT_proc1_V3.pdf |
[Irappa M. Halagali 1]