Tutorial 6: Study and Implementation of Digital Noise Source

Author: Kaushal Buch (Version 1)

Expected completion time: 2 hours

In this tutorial, you will study the concept of the digital noise source and implement it using the Simulink-System Generator based tool-flow & CASPER library. You will download the BORPH (.bof ) executable file on ROACH and will view the noise histogram on a P.C. by running a python script.

Click here for Complete information of Turorial Lab & Setup at Casper Workshop 2011, Pune, India. The lab at the workshop is pre-configured with the CASPER libraries, Matlab and Xilinx tools. If you want to try this tutorial in your lab, please refer the topics : H/W & S/W requirements and SET-UP of Tutorials at WORKSHOP 2011 ,Compiling the Design & Programming on ROACH FPGA and Locations & Files information for the WORKSHOP 2011 wherever applicable in the link Complete information of Turorial Lab & Setup.

Noise sources are required for the testing of hardware in absence of an actual input or in general to emulate the behaviour of noise. During the development of digital receiver design for radio telescopes, noise source is required for testing or, one has to check it, taking the output from the antenna (i.e. the actual operational receiver chain). The aim of this tutorial is to study and implement a digital noise source using the CASPER tool flow. A digital noise source can be implemented as a part of the receiver hardware which can be used to provide noise stimulus for verifying the digital design (correlator) on FPGA.

Various methods exist for generating Gaussian random numbers on hardware. We would be considering the use of Central Limit Theorem to generate Gaussian random numbers (noise) from random numbers with uniform probability distribution. The hardware requirement is relatively lesser for this approach and also it does not use any FPGA specific hardware like BRAM, multipliers etc.

Central Limit Theorem (CLT) states that when finite variance random variables having different phases are combined, it leads to random variable possessing a Gaussian distribution.

Uniform random number can be generated digitally using a Linear Feedback Shift Register. A maximal length LFSR can generate uniform random variables with a periodicity of 2ⁿ – 1, where n is the order of the polynomial. An example of x⁴ + x³ + 1 polynomial using LFSR is shown in the figure below -

The polynomial has to be chosen from the set of maximal length sequences, similar to ones used for generation of PN sequences in CDMA transmitter. Irreducible polynomials of degree L generate sequences whose periods must be divisors of q^L – 1. Those special irreducible polynomials, which are the characteristic polynomials of m-sequences, are called primitive polynomials, and they exist for every degree over every finite field.

A variant of the normal serial output LFSR known as the Leap Forward LFSR is used. The leap forward LFSR would generate a parallel output, by ‘looking-ahead’ number of bits required by the output vector. In our case, 14 LFSRs each having a periodicity of 2¹⁸-1 values, each of 4-bit are chosen for implementation.

Start Matlab and open Simulink (either by typing simulink on the Matlab command line, or by click in the Simulink icon in the taskbar). Open a new .mdl file and start the design with an LFSR.

Add a register from the library. Double click the register and select the synchronous reset port option.

The LFSR structure needs a feedback and Simulink requires an assert block when the output is fed back to the input. Connect the 'Assert' block at the output of the register and double click and set the output data type to Unsigned 1_0 (1 bit, binary point 0).

As we are designing for an 18-bit polynomial, we would require a bank of 18 registers.

Press Ctrl+A and drag the selection holding the ‘Ctrl’ key to duplicate a module. This process has to repeated till there are a total of 18 register banks.

Label your design as shown below -

For leap forwarding to get parallel outputs from the LFSR, we need to add XORing logic. Add an Expression block from the Xilinx library and double click to change the expression to a ^ b. Keep the output type to “Full”.

Using the expression blocks, create a structure for the LSB of the output as shown in the figure below.

Similarly, repeat it for all the other outputs as shown in figure below.

Concatenate the bits to get 4-bit output and also provide an input port for reset.

Create a subsystem for this LFSR block (by selecting the entire logic and using right click to 'Create Subsystem'.

Make sure to include In1 and Out1 blocks to assign ports to the subsystem. Once the subsystem is created, right click on the block and go to 'Mask Subsystem'. On clicking it, a window will open. Click on the first tab on the left column to add a new field in the table. Go to the 'Parameters' tab and add 'Seed' in the 'Prompt' field of the parameters. The variable would be set to 'seed' and Type to 'edit' and tick the 'Evaluate' and 'Tunable' field.

Now go to the initialization tab in the same window. In the field Dialog Variables, put 'seed' and in Initialization commands, paste (Cntrl+Y) the following line -

[s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18] = seed_value(seed);

Steps mentioned above provide the seed value to the LFSR. This would be passed through a Matlab function, the file containing this Matlab function (seed_value.m). This file must be copied in your working directory of MATLAB.

Right click the subsystem block and select 'Look Under Mask'. Double click the register block, starting from the top, and add the Initial value from s1 to s18 respectively in all the registers.

We have one noise source ready. In order to check the probability distribution of this source, we will first have to pass a seed from the top level subsystem and also we will need to store the data into a memory in order to be read through a PC and analyzed.

Make sure you re-check the labeling and block parameters carefully in this section as next step is duplicating these blocks and the error might propagate!

Take the LFSR block you have made and duplicate it till there are a total of 14 LFSR blocks. This should look like the figure below:

Construct the Adder tree as shown in figure:

As the input to the adder tree is Unsigned 4_0, the set the Output Type of the first stage of the adder should be Unsigned 5_0. The subsequent adder stages should be Unsigned 6_0. 7_0 and 8_0 respectively. Add a mux of 5 inputs with output type Unsigned 8_0.

The next setup should resemble the figure below:

Note: Don't forget to provide input and output ports (In1 and Out1)

Set constant value to 105 (Unsigned 8_0). Set AddSub block in Subtraction operation and Output type as Signed 8_0.

Now lets create a Noise Source subsystem that contains the LFSR bank and adder tree. To make a subsystem- select all (Cntrl+A), right click and then click Create Subsystem. As explained earlier, right click the subsystem and go to 'Mask Subsytem'. Add new field and add the details as shown in figure below –

Fill in the prompt parameter with Seed 1 to Seed 14 and variable parameter with seed1 to seed14. Enter the Subsystem and label LSFR's with seed1 to seed14.

Now double click the Noise Source subsystem and add random numbers as shown in the snapshot below -

Now, we need to provide reset to the circuit using software register, so add a software register, followed by a bit slice. Steps for selecting LSB of input: Double Click the bit slice block and tick the boolean output; 'specify range', 'lower bit location + width' and 'Offset of bottom bit' as 0 and select the option 'relative to LSB of input'. Please name the register 'reset'. You may add a Pulse Generator to the sim_in input of the software register. To store the generated random number samples, add a snap block from the CASPER library. Double click the snap block enter No. of Samples 2^16. This block will need trigger and write enable inputs. Provide write enable as a constant boolean input using a 'Constant' block. Trigger input can be provide similar to the reset but by adding a register (name it 'trig') followed by a rising-edge detector block. Also add the ROACH XSG Core Config (Setting: Clock pin location d7) and System Generator tokens (Setting: ROACH:sx95t,sys_clk, Sample Period-1, XST).

By giving bee_xps command in the matlab window we will get a pop-up. Make sure the file displayed in the pop-up is correct and then press RUN to start the compilation. After compilation , it creates a directory named after the model file name except .mdl and another sub directy as bit_files. In this bit_files directory there are .bit and .bof file. We need the .bof file to program the FPGA. You need to copy this .bof file at location [FPGA_PROG_BOF_DIR] after changing the permissions of the file.

eg. for the bof file [TUT6_BOF_FILE] in the area [STD_BOF_DIR]

$ chmod a+x [STD_BOF_DIR]/[TUT6_BOF_FILE]

$ cp [STD_BOF_DIR]/[TUT6_BOF_FILE] [FPGA_PROG_BOF_DIR]

The python scripts are located in the “[STD_PYSCRIPT_DIR]” directory. We first need to run “[TUT6_PYSCRIPT_FILE]” to program the FPGA and plot the result.

Usage : [STD_PYSCRIPT_DIR]/[TUT6_PYSCRIPT_FILE] <ROACH name/IP> -b

eg.

$ [STD_PYSCRIPT_DIR]/[TUT6_PYSCRIPT_FILE] roach030172 -b [tut6_digital_noise_src_2011_Sep_23_1128.bof]

             Enter the corresponding Location/File names and roach name/IP.

On the running above script, for a single noise source, a window showing the histogram of uniform distribution would appear as shown in the figure below -

The purpose of this tutorial is to develop a random number generator and also to understand the Central Limit Theorem, the concept behind generation of Gaussian distribution from uniform distribution. In order to view the distribution, we will vary the number of LFSR blocks so that the data from the random number generator can be monitored. By changing the multiplexer (mux_sel) value from 0-5 we can vary number of LFSR outputs that would be added to give the final output.

To change the value of mux_sel register, open the [TUT6_PYSCRIPT_FILE] and change the parameter passed to the register through the following line :

my_corr.write_int("mux_sel",0)

For a single noise source (mux_sel set to 0), a window showing the histogram of uniform distribution would appear as shown in the figure below:

The output after adding two LFSRs (mux_sel set to 1) (uniform number generators) should be as shown in the figure:

This tutorial discussed the basics of digital noise source designed using combination of uniform random number generators. It was shown how to implement a digital noise source using the CASPER tool-flow and test it on ROACH board. The noise data was read from the FPGA to generate histogram to see the distribution of noise and also to understand the Central Limit Theorem.