Adc083000 - david-macmahon/wiki_convert_test GitHub Wiki
Simulink (User) Outputs
- 8 lanes of 8-bit data, of Simulink type Fix_8_7.
- 4 "syncs" for each cycle of the clock signal output from the ADC board, each corresponding to a different cycle of the original undivided clock (which cycle is indicated by the signal index) original un-divided clock signal
- 4 "out of range" signals to indicate either positive or negative value saturation (must examine data to determine which) in the same orientation as the sync signals
- 1 data valid signal. Self explanatory name.
DCM Phase Adjustment
There have been reports of stability issues at higher ADC clock rates (>350MHz). Adjusting the DCM phase seems to solve the problem.
The DCM phase can be manually tuned by changing two lines of Verilog.
In xps_lib, navigate to:
XPS_ROACH_base/pcores/adc083000x2_interface_v1_00_a/hdl/verilog
Open these three files:
adc083000_board_phy.v
adc083000_board_phy_demux.v
adc083000_demux_interface.v
Find these two lines in each file:
.CLKOUT_PHASE_SHIFT("NONE")
.PHASE_SHIFT(0)
Change "NONE" to "FIXED", and set PHASE_SHIFT to 30.
The PHASE_SHIFT parameter can range from -255 to 255, but tests indicate that 30 is the optimal setting.
Pcore Architecture
LVDS Data => IBUFDS => DDR Register => IORegister => IORegister => Asynchronous FIFO => Simulink
Hopefully a diagram will be soon to follow.
Future Features (to be implemented)
- Serial interface
- The main ADC chip supports a serial interface to set phase/gains for the two sub-ADCs, which are interleaved together for the user to form