ADC1x3000 8 - david-macmahon/wiki_convert_test GitHub Wiki
Specifications
- ADC
- 1x National Semiconductor ADC083000 8-bit 3Gs/s ADC
- Board Schematic
I/O
- Inputs
- Referencing the above picture of the board, the input signals
must be connected via SMA connectors in the following order, top
to bottom:
- Clock: Maximum clock rate is 1.5 GHz, input sine wave. In testing work, a 0 dBm clock was used; no other clock powers were tested. The clock is divided down by 4 before going into the FPGA. Consequently, the data is also demuxed by 4, resulting in 8 simultaneous samples.
- Signal: Self-explanatory.
- Sync: This interface is set up to capture on all 4 phases of the clock generated by the DCM. The consequence of this is that so that in Simulink a user can determine exactly which cycle of the original board input clock the external sync pulse arrived. However, due to a lack of sync-pulse-generating equipment, this has not been tested.
- Referencing the above picture of the board, the input signals
must be connected via SMA connectors in the following order, top
to bottom:
- Outputs
- 1x Tyco Z-DOK+ 40
differential pair connector
- 4x 8-bit offset binary data @ DDR
- 1x digital clock to CASPER standard Z-DOK clock pins
- 1x Tyco Z-DOK+ 40
differential pair connector
Characterization
Software/Firmware interfacing
- Simulink Interface
- The simulink interface is via the block
'adc083000', named after the board's
center chip. The block outputs to users
- 8 lanes of 8-bit data
- 4 "syncs" for each cycle of the clock signal output from the ADC board, each corresponding to a different cycle of the original undivided clock (which cycle is indicated by the signal index) original un-divided clock signal
- 4 "out of range" signals to indicate either positive or negative value saturation (must examine data to determine which) in the same orientation as the sync signals
- 1 data valid signal. Self explanatory name.
- The simulink interface is via the block
'adc083000', named after the board's
center chip. The block outputs to users
- Control/Config
- The Simulink interface does not instantiate the 'obp_adccontroller' block (edited 08/14/2009) as software control of DCM is unnecessary, the phase/gain matching of the dual internal ADCs is sufficient for lab bench purposes, and the serial interface has not been set up. Modification of the pcore will be necessary to set up the serial interface. The board requires the use of an SPI, which the user may desire to operate from the linux terminal via borph.
Frequency Reponse
The frequency response of the National ADC083000 was performed with an Agilent signal generator (test tone), Tektronix signal generator (clock), and a ROACH board (data capture). There was -20dB attenuation on the input of the ADC and the Agilent signal generator output was 20dBm. We clocked the ADC at 800MHz, allowing us to sample at 1.6GS/s. The test tone was ranged from 0 - 3GHz, with any frequencies above 800MHz being aliased down. The raw 8bit ADC levels were captured in shared memory and read out using KATCP. As you can see from the plots below, serious roll off begins after about 2.4 GHz. The ADC board used was PCB v2.0, S/N 019, Fab R271 Rev 1. The ADC chip on this board was National Part # ADC083000C1YB, Date Code 44-09
