SH ISA - cr88192/bgbtech_shxemu GitHub Wiki

Registers:

  • Registers will be 32 bits.
  • R0..R15: General-Purpose Registers
    • R15/SP: Stack Pointer
  • SR: Status Register
  • GBR: Global Base Register
  • VBR: Vector Base Register
  • SSR: Saved Status Register
  • SPC: Saved PC
  • DBR: Debug Base Register
  • MACH: Multiply-Accumulate High
  • MACL: Multiply-Accumulate Low
  • PR: Procedure Register (Call/Return)
  • FPSCR: FPU Control Register
  • FPUL: FPU Load Register
  • FR0..FR15: FPU Registers
  • R0_A..R7_A: R0..R7 (Bank A, User)
  • R0_B..R7_B: R0..R7 (Bank B, Super)
Transistions between user and supervisor mode Flip Banks A and B. User or Supervisor mode determines which bank R0..R7 map to.

Interrupt:

  • Saves PC in SPC
  • Saves SR in SSR
  • Sets supervisor mode.
    • This swaps the register banks.
  • Loads address from its offset relative to VBR into PC.
  • Return from ISR swaps register banks, and restores SR and PC.
SR Bits:
  • 0000_0001: T //True/False Bit
  • 0000_0002: S //Specifies MAC Saturation
  • 0000_00F0: IM //Interrupt Level Mask
  • 0000_0100: Q //Q Bit (Divide)
  • 0000_0200: M //M Bit (Divide)
  • 0000_8000: FD //FPU Disable
  • 1000_0000: BL //Block Interrupts
  • 2000_0000: RB //Register Bank Select
  • 4000_0000: MD //User/Supervisor
FPSCR bits:
  • 0000_0003: RM //Rounding Mode
  • 0004_0000: DN //Denormalization Mode
  • 0008_0000: PR //Precision
  • 0010_0000: SZ //Load/Store Size
  • 0020_0000: FR //Float Register Bank
Address Space:
  • Unsigned 29 or 32 bit.
    • SH-2 Mode uses a 32-bit space
    • SH-4 Mode uses a 29-bit space
      • High 3 bits of address indicate access mode.
      • 0/1/2/3: User-Mode, Cache+MMU
      • 4: Cache, No MMU
      • 5: Non-Cache, No MMU
      • 6: Cache, MMU
      • 7: Non-Cache, Special
FPU:
  • FPU Registers are 32-bit and hold single or split-double values
  • The FPUSCR.SZ bit controls whether to copy a single or register pair.
  • The FPUSCR.PR bit selects between Single and Split-Double calculations.
MMU: An MMU may be used. It will be based on page-tables.

A 32-bit page table will be two level, with each page consisting of 1024 entries (1024*1024*4096=4GB).

Note that this is NOT the standard SH MMU.

Delay Slot: For branches, the instruction immediately following the branch is located in a "delay slot". This instruction will execute prior to the jump landing at the target. Branches and PC relative operations are not allowed in this space. However, BT and BF will not execute the delay-slot instruction.

For PC relative instructions, the calculation will be performed relative to 4 bytes after the PC of the instruction.

Opcode Size Suffixes:

  • .B, Byte (8-bit)
  • .W, Word (16-bit)
  • .L, DWord (32-bit)
Normal instructions will be 16 bit, and are expressed in nibbles.
  • 0..9, A..F: Expresses a literal hex value.
  • m: Expresses a source register.
  • n: Expresses a destination register.
  • M: Expresses a source register as 0-7 with high-bit set.
  • N: Expresses a destination register as 0-7 with high-bit set.
  • d: Expresses a displacement.
  • i: Expresses an immediate value (signed)
  • j: Expresses an immediate value (unsigned)
The endianess of instructions and PC-relative loads will always match the machine endianess. Loads performed relative to registers will use the local endianess.

If an instruction is preceded with a '/', it is not implemented, but more just to say what is there.

Instructions precded with '!' are extensions specific to this VM.

  • '!?', possible, but debatable.
  • '!!', very uncertain.
  • 0---
    • 0--0 RES (32-bit ops)
    • 0--1 RES (32-bit ops)
    • 0--2
      • 0n02 STC SR, Rn //Copy SR to Rn
      • 0n12 STC GBR, Rn //Copy GBR to Rn
      • 0n22 STC VBR, Rn //Copy VBR to Rn
      • 0n32 STC SSR, Rn //Copy SSR to Rn
      • 0n42 STC SPC, Rn //Copy SPC to Rn
      • 0n52 / STC ?, Rn //Copy DBR to Rn
      • 0-62 -
      • 0-72 -
      • 0nM2 STC Rm_B, Rn //Copy Rm_B to Rn (Other Bank)
    • 0--3
      • 0m03 BSRF Rm //Branch to Subroutine (PC+Rm+4)
      • 0-13 -
      • 0m23 BSAF Rm //Branch to Label (PC+Rn+4)
      • ..
      • 0n63 / MOVLI.L @Rm, R0 //MOV Linked
      • 0n73 / MOVCO.L R0, @Rn //MOV Conditional
      • 0n83 PREF @Rn //Prefetch memory for address
      • 0n93 / OCBI @Rn //Invalidate cache address without writeback
      • 0nA3 / OCBP @Rn //
      • 0nB3 / OCBWB @Rn
      • 0nC3 MOVCA.L R0, Rn
      • 0nE3 / ICBI @Rn //Invalidates I-Cache at Address
    • 0nm4 MOV.B Rm, @(R0,Rn) //Move Byte Rm to R0+Rn
    • 0nm5 MOV.W Rm, @(R0,Rn) //Move Word Rm to R0+Rn
    • 0nm6 MOV.L Rm, @(R0,Rn) //Move DWord Rm to R0+Rn
    • 0nm7 MUL.L Rm, Rn //Multiply Rm and Rn and store MACL
    • 0--8 //Operations without arguments
      • 0008 CLRT //Clear SR.T
      • 0018 SETT //Set SR.T
      • 0028 CLRMAC //Clear MACH and MACL
      • 0038 / LDTLB //LDTLB (Not Used)
      • 0048 CLRS //Clear SR.S
      • 0058 SETS //Set SR.S
      • 0068 / NOTT
    • 0--9
      • 0009 NOP //NOP
      • 0019 DIV0U //Unsigned Divide
      • 0n29 MOVT Rn //Copy T bit to Rn
      • 0n39 / MOVRT Rn
      • 0mA9 / MOVUA.L @Rm, R0 //MOV Unaligned
      • 0mE9 / MOVUA.L @Rm+, R0 //MOV Unaligned
    • 0--A
      • 0n0A STS MACH, Rn //Copy MACH to Rn
      • 0n1A STS MACL, Rn //Copy MACL to Rn
      • 0n2A STS PR, Rn //Copy PR to Rn
      • 0n3A STC SGR, Rn
      • 0n4A / STC ?, Rn
      • 0n5A STS FPUL, Rn //Copy FPUL to Rn
      • 0n6A STS FPSCR, Rn //Copy FPSCR to Rn
    • 0--B
      • 000B RTS //Return from Function
      • 001B SLEEP //Sleep until interrupt
      • 002B RTE //Return From Exception
      • 003B BRK //Breakpoint Exception
      • 004B -
      • 005B / RESBANK
      • 006B / RTS/N
      • 0m7B / RTV/N Rm
      • 00AB / SYNCO //Delay until all preceding operations complete
      • ...
    • 0nmC MOV.B @(R0,Rm), Rn //Load Byte From R0+Rm into Rn
    • 0nmD MOV.W @(R0,Rm), Rn //Load Word From R0+Rm into Rn
    • 0nmE MOV.L @(R0,Rm), Rn //Load DWord From R0+Rm into Rn
    • 0nmF MAC.L @Rm, @Rn //Load/Mul Rm and Rn and add to MACH/MACL
  • 1nmd MOV.L Rm, @(Rn,disp) //Store DWord Rm to Rn+4*Disp
  • 2---
    • 2nm0 MOV.B Rm, @Rn //Store Byte Rm to @Rn
    • 2nm1 MOV.W Rm, @Rn //Store Word Rm to @Rn
    • 2nm2 MOV.L Rm, @Rn //Store Rm to @Rn
    • 2nm3 CAS.L Rm, Rn, @R0 //Compare and Exchange
    • 2nm4 MOV.B Rm, @-Rn //Store Rm to Byte @Rn then Rn=Rn-1
    • 2nm5 MOV.W Rm, @-Rn //Store Rm to Word @Rn then Rn=Rn-2|8
    • 2nm6 MOV.L Rm, @-Rn //Store Rm to DWord @Rn then Rn=Rn-4
    • 2nm7 DIV0S Rm, Rn //Setup for signed division
    • 2nm8 TST Rm, Rn //Test Rm&Rn, updating SR.T
    • 2nm9 AND Rm, Rn //And Rm and Rn, Storing result in Rn
    • 2nmA XOR Rm, Rn //Xor Rm and Rn, Storing result in Rn
    • 2nmB OR Rm, Rn //Or Rm and Rn, Storing result in Rn
    • 2nmC CMPSTR Rm, Rn //Compare Rm and Rn for matching bytes
    • 2nmD XTRCT Rm, Rn //Low bits from Rm and High bits from Rn
    • 2nmE MULU.W Rm, Rn //Multiply Unsigned Word/DWord, Dst=MACL
    • 2nmF MULS.W Rm, Rn //Multiply Signed Word/DWord, Dst=MACL
  • 3---
    • 3nm0 CMPEQ Rm, Rn //Compare for Equality
    • 3--1 RES (32-bit ops)
    • 3nm2 CMPHS Rm, Rn //Compare for unsigned Greater/Equal
    • 3nm3 CMPGE Rm, Rn //Compare for signed Greater/Equal
    • 3nm4 DIV1 Rm, Rn //Inner part of divide
    • 3nm5 DMULU.L Rm, Rn //Unsigned Multiply, result in MACH:MACL
    • 3nm6 CMPHI Rm, Rn //Compare for unsigned Greater
    • 3nm7 CMPGT Rm, Rn //Compare for signed Greater
    • 3nm8 SUB Rm, Rn //Subtract
    • 3--9 RES (32-bit ops)
    • 3nmA SUBC Rm, Rn //Subtract, Carry -> T
    • 3nmB SUBV Rm, Rn //Subtract, Overflow -> T
    • 3nmC ADD Rm, Rn //Add
    • 3nmD DMULS.L Rm, Rn //Signed Multiply, result in MACH:MACL
    • 3nmE ADDC Rm, Rn //Add with Carry, Carry -> T
    • 3nmF ADDV Rm, Rn //Add, Overflow -> T
  • 4---
    • 4--0
      • 4n00 SHLL Rn
      • 4n10 DT Rn
      • 4n20 SHAL Rn
      • 4n80 / MULR R0, Rn
      • 4mF0 / MOVMU.L Rm, @-R15
    • 4--1
      • 4n01 SHLR Rn
      • 4n11 CMPPZ Rn
      • 4n21 SHAR Rn
      • ..
      • 4n81 / CLIPU.B
      • 4n91 / CLIPS.B
      • 4nE1 / STBANK r0, @Rn
      • 4mF1 / MOVML.L Rm, @-R15
    • 4--2
      • 4n02 STS.L MACH, @-Rn
      • 4n12 STS.L MACL, @-Rn
      • 4n22 STS.L PR, @-Rn
      • 4n32 STC.L SGR, @-Rn
      • 4n42 / STC.L ?, @-Rn
      • 4n52 STS.L FPUL, @-Rn
      • 4n62 STS.L FPSCR, @-Rn
      • 4-72 -
      • ..
      • 4-F2 -
    • 4--3
      • 4n03 STC.L SR, @-Rn
      • 4n13 STC.L GBR, @-Rn
      • 4n23 STC.L VBR, @-Rn
      • 4n43 STC.L SSR, @-Rn
      • 4n53 STC.L SPC, @-Rn
      • 4n63 / STC.L ?, @-Rn
      • 4-63 -
      • 4-73 -
      • 4nM3 STC.L Rm_B, @-Rn
    • 4--4
      • 4n04 ROTL Rn
      • 4-14 -
      • 4-24 ROTCL Rn
      • 4-34 -
      • 4n44 -
      • 4n54 -
      • ..
      • 4n84 / DIVU R0, Rn
      • 4n94 / DIVS R0, Rn
      • ..
      • 4-F4
      • 4nF4 / MOVMU.L @R15+, Rn
    • 4--5
      • 4n05 ROTR Rn
      • 4n15 CMPPL Rn
      • 4n25 ROTCR Rn
      • ..
      • 4n85 / CLIPU.W
      • 4n95 / CLIPS.W
      • ..
      • 4mE5 / LDBANK @Rm, R0
      • 4nF5 / MOVML.L @R15+, Rn
    • 4--6
      • 4m06 LDS.L @Rm+, MACH
      • 4m16 LDS.L @Rm+, MACL
      • 4m26 LDS.L @Rm+, PR
      • 4m36 LDC.L @Rm+, SGR
      • 4m46 / LDC.L @Rm+, ?
      • 4m56 LDS.L @Rm+, FPUL
      • 4m66 LDS.L @Rm+, FPSCR
      • 4-76 -
      • ..
      • 4-F6 -
    • 4--7
      • 4m07 LDC.L @Rm+, SR
      • 4m17 LDC.L @Rm+, GBR
      • 4m27 LDC.L @Rm+, VBR
      • 4m37 LDC.L @Rm+, SSR
      • 4m47 LDC.L @Rm+, SPC
      • 4m57 / LDC.L @Rm+, ?
      • 4-67 -
      • 4-77 -
      • 4mN7 LDC.L @Rm+, Rm_B
    • 4--8
      • 4n08 SHLL2 Rn
      • 4n18 SHLL8 Rn
      • 4n28 SHLL16 Rn
    • 4--9
      • 4n09 SHLR2 Rn
      • 4n19 SHLR8 Rn
      • 4n29 SHLR16 Rn
      • 4mA9 / MOVUA.L @Rm, R0
      • 4mE9 / MOVUA.L @Rm+, R0
    • 4--A
      • 4m0A LDS Rm, MACH
      • 4m1A LDS Rm, MACL
      • 4m2A LDS Rm, PR
      • 4m3A LDC Rm, SGR
      • 4m4A / LDC Rm, ?
      • 4m5A LDS Rm, FPUL
      • 4m6A LDS Rm, FPSCR
      • 4-7A -
      • ..
      • 4-FA -
    • 4--B
      • 4m0B JSR Rm
      • 4m1B TAS.B Rm
      • 4m2B JMP Rm
      • ..
      • 4m4B / JSR/N
      • ..
      • 4m8B / MOV.B R0, @Rn+
      • 4m9B / MOV.W R0, @Rn+
      • 4mAB / MOV.L R0, @Rn+
      • 4mCB / MOV.B @-Rm, R0
      • 4mDB / MOV.W @-Rm, R0
      • 4mEB / MOV.L @-Rm, R0
      • 4-FB -
    • 4nmC SHAD Rm, Rn
    • 4nmD SHLD Rm, Rn
    • 4--E
      • 4m0E LDC Rm, SR
      • 4m1E LDC Rm, GBR
      • 4m2E LDC Rm, VBR
      • 4m3E LDC Rm, SSR
      • 4m4E LDC Rm, SPC
      • 4m5E / LDC Rm, ?
      • 4-6E -
      • 4-7E -
      • 4mNE LDC Rm, Rm_B
    • 4nmF MAC.W/Q Rm, Rn
  • 5nmd MOV.L @(Rm,disp), Rn
  • 6---
    • 6nm0 MOV.B @Rm, Rn
    • 6nm1 MOV.W @Rm, Rn
    • 6nm2 MOV.L @Rm, Rn
    • 6nm3 MOV Rm, Rn
    • 6nm4 MOV.B @Rm+, Rn
    • 6nm5 MOV.W @Rm+, Rn
    • 6nm6 MOV.L @Rm+, Rn
    • 6nm7 NOT Rm, Rn
    • 6nm8 SWAP.B @Rm, Rn
    • 6nm9 SWAP.W @Rm, Rn
    • 6nmA NEGC Rm, Rn
    • 6nmB NEG Rm, Rn
    • 6nmC EXTU.B Rm, Rn
    • 6nmD EXTS.B Rm, Rn
    • 6nmE EXTU.W Rm, Rn
    • 6nmF EXTS.W Rm, Rn
  • 7nii ADD #imm, Rn
  • 8---
    • 80nd MOV.B R0, @(Rn,disp)
    • 81nd MOV.W R0, @(Rn,disp)
    • 82-- -
    • 83-- / JSR/N
    • 84md MOV.B @(Rm,disp), R0
    • 85md MOV.W @(Rm,disp), R0
    • 86-- / BSET|BCLR #imm3, Rn
    • 87-- / BST|BLD #imm3, Rn
    • 88ii CMPEQ #imm, R0
    • 89dd BT label
    • 8A-- ! MOVI24 #imm24, R0 //32-bit op, loads 24-bit immediate.
    • 8Bdd BF label
    • 8Cii ! LDSH8 #imm, R0 //R0=(R0 SHL 8)|Imm8
    • 8Ddd BTS label
    • 8Eii ! XPFX0 //Combiner Prefix (BJX ISA)
      • Combines with a following instruction to form a new one.
    • 8Fdd BFS label
  • 9ndd MOV.W @(PC,disp), Rn
  • Addd BRA label
  • Bddd BSR label
  • C---
    • C0dd MOV.B R0, @(GBR,disp)
    • C1dd MOV.W R0, @(GBR,disp)
    • C2dd MOV.L R0, @(GBR,disp)
    • C3jj TRAPA #imm
    • C4dd MOV.B @(GBR,disp), R0
    • C5dd MOV.W @(GBR,disp), R0
    • C6dd MOV.L @(GBR,disp), R0
    • C7dd MOVA @(PC,disp), R0 //Load Address into R0, Dword aligned.
    • C8jj TST #imm, R0
    • C9jj AND #imm, R0
    • CAjj XOR #imm, R0
    • CBjj OR #imm, R0
    • CCjj TST.B #imm, @(GBR,R0)
    • CDjj AND.B #imm, @(GBR,R0)
    • CEjj XOR.B #imm, @(GBR,R0)
    • CFjj OR.B #imm, @(GBR,R0)
  • Dndd MOV.L @(PC,disp), Rn //Load DWord, DWord aligned.
  • Enii MOV #imm, Rn //Load immediate into register.
  • F---
    • Fnm0 FADD FRm, FRn
    • Fnm1 FSUB FRm, FRn
    • Fnm2 FMUL FRm, FRn
    • Fnm3 FDIV FRm, FRn
    • Fnm4 FCMPEQ FRm, FRn
    • Fnm5 FCMPGT FRm, FRn
    • Fnm6 FMOV.S @(R0,Rm), FRn
    • Fnm7 FMOV.S FRm, @(R0,Rn)
    • Fnm8 FMOV.S @Rm, FRn
    • Fnm9 FMOV.S @Rm+, FRn
    • FnmA FMOV.S FRm, @Rn
    • FnmB FMOV.S FRm, @-Rn
    • FnmC FMOV FRm, FRn
    • F--D
      • Fn0D FSTS FRn
      • Fm1D FLDS FRm
      • Fn2D FLOAT FRn
      • Fm3D FTRC FRm
      • Fn4D FNEG FRn
      • Fn5D FABS FRn
      • Fn6D FSQRT FRn
      • F-7D / FSRRA
      • Fn8D FLDI0 FRn //Load 0.0
      • Fn9D FLDI1 FRn //Load 1.0
      • FnAD FCNVSD FRn
      • FnBD FCNVDS FRm
      • F-CD -
      • F-DD -
      • F-ED / FIPR
      • F-FD
        • F0FD / FSCA //Sin/Cos
        • F1FD / FTRV2
        • F2FD / FSCA //
        • F3FD FSCHG //Flips FPSCR.SZ
        • F4FD / FSCA //
        • F5FD / FTRV2
        • F6FD / FSCA //
        • F7FD / FPCHG //Flips FPSCR.PR
        • F8FD / FSCA //
        • F9FD / FTRV2
        • FAFD / FSCA //
        • FBFD / FRCHG //Flips FPSCR.FR
        • FCFD / FSCA //
        • FDFD / FTRV2
        • FEFD / FSCA //
    • FnmE FMAC FRm, FRn
    • F--F ! (BT RES-32)
32-bit I-Forms (currently unsupported, reserved):
  • 0ni0-iiii MOVI20 #imm, Rn
  • 0ni1-iiii MOVI20S #imm, Rn
  • 3nm1-0ddd MOV.B Rm, @(Rn, disp)
  • 3nm1-1ddd MOV.W Rm, @(Rn, disp)
  • 3nm1-2ddd MOV.L Rm, @(Rn, disp)
  • 3nm1-3ddd FMOV.S FRm, @(Rn, disp)
  • 3nm1-4ddd MOV.B @(Rm, disp), Rn
  • 3nm1-5ddd MOV.W @(Rm, disp), Rn
  • 3nm1-6ddd MOV.L @(Rm, disp), Rn
  • 3nm1-7ddd FMOV.S @(Rm, disp), FRn
  • 3nm1-8ddd MOVU.B @(Rm, disp), Rn
  • 3nm1-9ddd MOVU.W @(Rm, disp), Rn
  • 3ni9-0ddd BCLR.B
  • 3ni9-1ddd BSET.B
  • 3ni9-2ddd BST.B
  • 3ni9-3ddd BLD.B
  • 3ni9-4ddd BAND.B
  • 3ni9-5ddd BOR.B
  • 3ni9-6ddd BXOR.B
  • 3ni9-Bddd BLDNOT.B
  • 3ni9-Cddd BANDNOT.B
  • 3ni9-Dddd BORNOT.B
BT 32-Bit
  • None
Super-Ops will be instructions that when placed adjacent may be treated as a single combined instruction. This combined unit will have equivalent external behavior to the sequence of component instructions.

Compare-Branch Super-Ops

  • 3nm0-89dd CMPBEQ Rm, Rn, label //compare-and-branch super-op
  • 3nm0-8Bdd CMPBNE Rm, Rn, label //if(Rn!=Rm)goto label;
  • 3nm3-89dd CMPBGE Rm, Rn, label //compare-and-branch super-op
  • 3nm3-8Bdd CMPBLT Rm, Rn, label
  • 3nm7-89dd CMPBGT Rm, Rn, label //compare-and-branch super-op
  • 3nm7-8Bdd CMPBLE Rm, Rn, label //if(Rn<=Rm)goto label;
  • Semantically equivalent to component ops.
Shift Super-Ops
  • Emii-4nmC SHAD #imm, Rm, Rn
  • Emii-4nmD SHLD #imm, Rm, Rn
  • Semantically equivalent to component ops.
    • Unlike combiner-form, this will store the immediate into Rm.
Extensions split off into a new ISA SH-BJX1-ISA
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