SH BJX1 ISA - cr88192/bgbtech_shxemu GitHub Wiki
ISA:
- This is a working spec for an extended version of the SH ISA.
- This is based mostly on SH4 (Hitachi SuperH)
- Details here are subject to change without warning.
- This spec will cover the 32 and 64-bit ISA.
Registers:
- Registers will be 32 or 64 bits.
- R0..R15: General-Purpose Registers
- R15/SP: Stack Pointer
- R16..R31: Extended General-Purpose Registers (BJX1-64A only)
- SR: Status Register
- GBR: Global Base Register
- VBR: Vector Base Register
- SSR: Saved Status Register
- SPC: Saved PC
- SGR: Saved R15/SP
- DBR: Debug Base Register
- MACH: Multiply-Accumulate High
- MACL: Multiply-Accumulate Low
- PR: Procedure Register (Call/Return)
- FPSCR: FPU Control Register
- FPUL: FPU Load Register
- PC: Program Counter
- FR0..FR15: FPU Registers (Bank A)
- XF0..XF15: FPU Registers (Bank B)
- YF0..YF15: FPU Registers (Bank C, N/A Basic FPU)
- ZF0..ZF15: FPU Registers (Bank D, N/A Basic FPU)
- R0_A..R7_A: R0..R7 (Bank A, User)
- R0_B..R7_B: R0..R7 (Bank B, Super)
- Transistions between user and supervisor mode Flip Banks A and B.
- User or Supervisor mode determines which bank R0..R7 map to.
- R16_A..R23_A: R16..R23 (Bank A, User, BJX1-64A)
- R16_B..R23_B: R16..R23 (Bank B, Super, BJX1-64A)
- R16 through R23 are also swapped in BJX1-64A.
- SR0, MACH
- SR1, MACL
- SR2, PR
- SR3, SGR
- SR4
- SR5, FPUL
- SR6, FPSCR
- SR7
- ..
- SR15, DBR
- CR0, SR
- CR1, GBR
- CR2, VBR
- CR3, SSR
- CR4, SPC
- CR5
- CR6
- CR7, PC
- CR8, MMUCR
- CR9, PTEH
- CR10, PTEL
- CR11, TTB
- CR12, TEA
- CR13, TRAEVT
- CR14, EXPEVT
- CR15, INTEVT
- Saves PC in SPC
- Saves SR in SSR
- Saves SP in SGR
- Sets supervisor mode.
- This swaps the register banks (Setting SR.RB).
- Set SR.JQ and SR.DQ according to SRH.TR_DQ and SRH.TR_JQ
- Loads an address as an offset relative to VBR into PC.
- Return from ISR swaps register banks, and restores SR and PC.
- 0000_0001: T //True/False Bit
- 0000_0002: S //Specifies MAC Saturation
- 0000_00F0: IM //Interrupt Level Mask
- 0000_0100: Q //Q Bit (Divide)
- 0000_0200: M //M Bit (Divide)
- 0000_0400: -
- 0000_0800: -
- 0000_1000: DQ //Data Quad
- 0000_2000: -
- 0000_4000: -
- 0000_8000: FD //FPU Disable
- 0FFF_0000: -
- 1000_0000: BL //Block Interrupts
- 2000_0000: RB //Register Bank Select
- 4000_0000: MD //User/Supervisor
- 8000_0000: JQ //Operate in 64-bit mode
- 0000_1000: TR_DQ //Trap Data Quad
- 8000_0000: TR_JQ //Trap 64-bit Mode
- 0000_0003: RM //Rounding Mode
- 0004_0000: DN //Denormalization Mode
- 0008_0000: PR //Precision
- 0010_0000: SZ //Load/Store Size
- 0020_0000: FR //Float Register Bank (Swap FRn/XFn)
- SR.JQ, SR.DQ, SRH.TR_JQ, SRH.TR_DQ
- These are reserved and Must Be Zero.
- SR.JQ will give the current logical operating mode.
- If clear, we are in 32-bit mode.
- If set, we are in 64-bit mode.
- SR.DQ sets the nominal operation size within 64-bit mode.
- If clear, operators work on 32-bit values.
- If set, operators work on 64-bit values.
- Some instruction forms may ignore DQ.
- SRH.TR_JQ and SRH.TR_DQ do similar, but for exception handlers.
- When an exception occurs, the mode is to be set according to these bits.
- In BJX1-64, TR_JQ may be required to be set.
Profiles:
- BJX1-32: Will be a 32-bit operating mode.
- Will contain the basic SH4 ISA as a subset.
- BJX1-64: Will be the 64-bit operating mode.
- BJX1-64A: Will contain most functionality from BJX1-64.
- BJX1-64B: Will only have R0-R15.
- BJX1-64u: Will be a subset only containing 16-bit instruction forms.
- Will only have R0-R15.
- Operation is mostly equivalent to SH4.
- Will support both 29 and 32-bit addressing.
- By default, the initial addressing mode will be 29 bit.
- Limited to the same register space as SH.
- SR.JQ and DQ will be invalid on BJX1-32 cores.
- Will boot directly in 64-bit mode, and use a different memory map.
- Uses a 48 bit address space with 40 bit external addresses.
- Boot: JQ=1, DQ=0.
Address Space (BJX1-32):
- Unsigned 29 or 32 bit virtual address space.
- AT=0, addresses map directly to the 29 bit physical space.
- AT=1, addresses are translated via an MMU.
- Uses a 29-bit physical address space
- High 3 bits of address indicate access mode.
- 0/1/2/3: User-Mode, Cache+MMU
- 4: Cache, No MMU
- 5: Non-Cache, No MMU
- 6: Cache, MMU
- 7: Non-Cache, Special
- A larger (32 bit) physical space may be supported, but only via the MMU.
- The low 29 bit range maps as before.
- Bits above the 29 bit mark may be mapped using pages.
- A basic physical memory MAP
- 0000_0000..001F_FFFF, Firmware
- 0020_0000..0BFF_FFFF, MMIO / Hardware
- 0C00_0000..0FFF_FFFF, Low RAM (64MB)
- 1000_0000..17FF_FFFF, Mid RAM (128MB)
- 1800_0000..1DFF_FFFF, High RAM (64-96MB)
- 1E00_0000..1EFF_FFFF, Chipset
- 1F00_0000..1FFF_FFFF, Memory Mapped Registers
- 2000_0000..9FFF_FFFF, More RAM
- A000_0000..EFFF_FFFF, More MMIO / Hardware
- FE00_0000..FEFF_FFFF, Chipset
- FF00_0000..FFFF_FFFF, Memory Mapped Registers
- May use a 32-bit or 48-bit virtual address space.
- For now, will define a 40 bit physical address space.
- Modified 32-bit Address Space (JQ=0, AT=1)
- 0000_0000..7FFF_FFFF: User, MMU
- 8000_0000..BFFF_FFFF: User/System, MMU
- C000_0000..DFFF_FFFF: System, MMU
- E000_0000..EFFF_FFFF: Chipset and MMIO
- F000_0000..FFFF_FFFF: Processor and Chipset
- 48-bit Address Space (JQ=1, AT=1)
- 0000_0000_0000..7FFF_FFFF_FFFF: User, MMU
- 8000_0000_0000..8000_FFFF_FFFF: 32-bit Space
- 8001_0000_0000..807F_FFFF_FFFF: External RAM
- 80A0_0000_0000..80DF_FFFF_FFFF: MMIO
- 9000_0000_0000..FFFF_FFFF_FFFF: System, MMU
- A basic physical memory MAP
- 00_0000_0000..00_FFFF_FFFF: Equivalent to BJX1-32 Ranges
- 10_0000_0000..9F_FFFF_FFFF: RAM (High Range)
- 10_0000_0000..10_FFFF_FFFF: Identity map with low-range RAM addresses.
- This range need only exist if target has more than 4GB of RAM.
- A0_0000_0000..DF_FFFF_FFFF: MMIO (High Range)
A 32-bit page table will be two level, with each page consisting of 1024 entries (1024*1024*4096=4GB).
Note that this is NOT the standard SH4 MMU model.
Note that the core "may" require system code to implement its own page-walking to TLB conversion, however:
- Only 4kB pages are allowed
- TLB state will be off-limits to user code.
- The system will be assumed to implement a normal page-table.
This will give a 48-bit logical address space, which is sign-extended to 64 bits.
Memory Mapped MMU Registers:
- Located at a physical base address of 1F00_0000 or FF00_0000.
- FF00_0000: PTEH (Page Table Entry High)
- FF00_0004: PTEL (Page Table Entry Low)
- FF00_0008: TTB (Translation Table Base)
- Used as the address of the active page table.
- FF00_000C: TEA (Translation Table Address)
- Used on page faults, holds virtual address of faulted access.
- Some other faults, holds the address which triggered the fault.
- FF00_0010: MMUCR (MMU Control Register)
- MMU Control Bits
- Bit 0: AT (Address Translation Enabled)
- Turns on address translation via a page table.
- Bit 2: TLB Invalidate
- Setting this bit will trigger the TLB to be flushed.
- Bit 8: SV (Single Virtual Address Mode)
- Serves mostly as a TLB policy hint in FMMU.
- All other bits reserved/undefined in FMMU.
- Bits 0..11: Reserved (Zeroed)
- Bits 12..31: Physical Page Address (of Page Table Directory)
- The Page Table Directory will consist of 1024 32-bit Page Directory Entries (PDE's).
- Each PDE will hold the physical address of a Page Table page, and will follow the same basic format as a PTE.
- Each Page Table will consist of 1024 32-bit Page Table Entries (PTE's).
- Each PTE will give the physical address of a data page.
- Not all entries need to be valid.
- Bit 0: WT (Write Through)
- 0=Copy Back
- 1=Write Through
- Bit 1: SH (Share Status)
- Indicates if a page is shared between multiple processes.
- 0=Local to a given process.
- 1=Shared between processes.
- Bit 2: D (Dirty)
- May be set if a page's contents have been modified.
- Bit 3: C (Cacheable)
- 0=Non-Cacheable
- 1=Cacheable
- Bit 4: SZ0 (Size Bit 0)
- Possible: PR.X (Execute Enable)
- Bit 5: PR.W (Write Enable)
- Page may be written to.
- Bit 6: PR.U (User Accessible)
- 0=Page only accessible in supervisor mode.
- 1=Page can be accessed in user mode.
- Bit 7: SZ1 (Size Bit 1)
- Bit 8: V (Present/Valid)
- Indicates an entry actually pointing at a page.
- 0=Entry is not present or not valid.
- If 0, then attempts to access this page should fault.
- All other bits are undefined, and may be used by the OS.
- 1=Entry is present and (should be) valid.
- Bit 9: User Bit 1 (For use by OS)
- Bit 10: User Bit 2 (For use by OS)
- Bit 11: User Bit 3 (For use by OS)
- Bit 12..31: PPN (Physical Page Number)
- In PTEs, these may only be set as (SZ0=1,SZ1=0), Indicating 4kB pages.
- Low order bits of the page number are reserved and are to be set to 0.
- All other combinations are reserved.
- 0000_0000 .. 7FFF_FFFF: Translated via page tables (2GB).
- 8000_0000 .. 9FFF_FFFF: Retains physical addressing.
- A000_0000 .. BFFF_FFFF: Retains physical addressing.
- C000_0000 .. DFFF_FFFF: Translated via the MMU (512MB).
- E000_0000 .. FFFF_FFFF: Reserved for processor/chipset.
- When a TLB miss happens, a ISR may be invoked.
- The ISR will load data from the page table into PTEL and PTEH.
- It will then use a LDTLB instruction, and return from the ISR.
Memory Mapped MMU Registers:
- FF00_0020: TRAEVT ( Trap Event )
- Bits 9:2 hold immediate from TRAPA instruction.
- FF00_0024: EXPEVT ( Exception Event )
- Low 12 bits hold hardware exception code.
- FF00_0028: INTEVT ( Interrupt Event )
- Low 12 bits hold hardware exception code.
- VBR+0x100: General Exception (Uses EXPEVT)
- VBR+0x400: TLB Exception (Uses EXPEVT)
- VBR+0x600: Hardware Interrupt (Uses INTEVT)
- 0x000: POWERON
- 0x020: MANRESET
- 0x040: RTLBMISS ( Read TLB Miss )
- 0x060: WTLBMISS ( Write TLB Miss )
- 0x080: FIRSTWRITE ( Writing to page with dirty bit clear )
- 0x0A0: READPROT ( Read Protection Error )
- 0x0C0: WRITEPROT ( Write Protection Error )
- 0x0E0: RADDERR ( Read Address Error )
- 0x100: WADDERR ( Write Address Error )
- 0x120: FPUEXC ( Floating Point Exception )
- 0x140: TLBMULTIHIT
- 0x160: TRAP ( Trap Instruction Used )
- 0x180: RESINST ( Reserved Instruction )
- 0x1A0: ILLSLOT (Invalid in Delay Slot )
- 0x1C0: NMI
- 0x1E0: UBRK ( User Breakpoint )
- 0x800: FPUDIS ( FPU Disabled )
- 0x820: SLOTFPUDIS ( FPU Disabled in Delay Slot )
- Saves PC in SPC
- Saves SR in SSR
- Saves SP in SGR
- Sets supervisor mode.
- Sets SR.MD and SR.BL to indicate supervisor mode.
- This swaps the register banks (Setting SR.RB).
- Loads an address as an offset relative to VBR into PC.
- Return from ISR restores SR and PC.
- This also returns to the prior register bank.
Delay Slot: For branches, the instruction immediately following the branch is located in a "delay slot". This instruction will execute prior to the jump landing at the target. Branches and PC relative operations are not allowed in this space. However, BT and BF will not execute the delay-slot instruction.
For PC relative instructions, the calculation will be performed relative to 4 bytes after the PC of the current instruction.
- Both Long and Quad operations will use a 32-bit alignment.
- For 32-bit instruction forms, this offset will be 6 bytes.
Note that 32-bit instruction forms will not be allowed in the delay slot.
Opcode Size Suffixes:
- .B, Byte (8-bit)
- .W, Word (16-bit)
- .L, DWord (32-bit)
- .Q, QWord (64-bit)
- .W/Q, Word or Quad (Depends on Mode, Usually SR.DQ)
- .L/Q, DWord or Quad (Depends on Mode, Usually SR.JQ)
- .Q/W, Quad or Word (Depends on Mode, Usually SR.DQ)
- Basically, the reverse of W/Q
- ./Q, DWord (No Suffix) or Quad (with suffix, if SR.DQ is Set)
- Registers will only preserve 32 bits.
- 0..9, A..F: Expresses a literal hex value.
- m: Expresses a source register.
- n: Expresses a destination register.
- M: Expresses a source register as 0-7 with high-bit set.
- N: Expresses a destination register as 0-7 with high-bit set.
- d: Expresses a displacement.
- i: Expresses an immediate value (signed).
- j: Expresses an immediate value (unsigned).
- k: Immediate Shift Value
- s: Source (Left) register.
- t: Source (Right) register.
- o: Offset or Index register.
- P/p: Source Register (m), 3-bit (Bit 3 set/clear)
- Q/q: Destination Register (n), 3-bit (Bit 3 set/clear)
- The 3 bit registers map to 0..6=R8..R14 and 7=R0
- Are normally scaled by the size of the data type.
- disp4, disp8, and disp12 are zero extended.
- disp8s is sign-extended.
- @Rm
- Access memory via address in Rm
- @Rm+
- Load from address in Rm, incrementing the address
- @-Rn
- Store to address given in Rn, first decrementing the address
- @(R0,Rm)
- Load or store to address given by R0+Rm
- @(PC,Rm)
- Load or store to address given by PC+Rm
- PC is typically the start address of the instruction +4.
- For 32-bit instructions, it is +6.
- @(GBR,disp)
- Memory access is GBR + a scaled displacement.
- @(Rm, disp)
- Address is Rm with a displacement scaled by the value size.
- @(Rm, Ro)
- Address is given by Rm+Ro*Scale
- If Ro is R0, then Scale is 1 (Byte).
- An Ro set to R15 is reserved/invalid.
- @(Rm, Ro, disp)
- Address is given by Rm+(Ro+Disp)*Scale
- If Ro is R0, then Scale is 1 (Byte).
- If Ro is R15, then Ro is treated as if it held 0.
If an instruction is preceded with a '/', it is not implemented, but more just to declare that a space is reserved for this instructions.
Instructions precded with '!' are extensions specific to this VM or ISA.
- '!?', possible, but debatable.
- '!!', very uncertain.
- '?', To Be Decided
- '_', Supported, but may have other limitations.
- 000n-nnnn //Shift Left N bits
- 111n-nnnn //Shift Right (32-N) bits
- 1110-0000 //All bits are bit 31
- Other cases will depend on sign and are mod32.
- 00nn-nnnn //Shift Left N bits
- 11nn-nnnn //Shift Right (64-N) bits
- 1100-0000 //All bits are bit 63
- Other cases will depend on sign and are mod64.
- Behaves the same as the 64-bit shift.
- The input is sign or zero extended to 64 bits prior to the shift.
- 00nn-nnnn //Shift Left N bits (Sign/Zero Extend)
- 01nn-nnnn //Shift Left N bits (64-bit)
- 10nn-nnnn //Shift Right (64-N) bits (64-bit)
- 11nn-nnnn //Shift Right (64-N) bits (Sign/Zero Extend)
- Behaves like SHLD with a positive shift
- Behaves like SHLD with a negative shift if shift>0
- 0 behaves like SHLD with 0
- Negative values are undefined.
- Behaves like SHAD with a negative shift if shift>0
- 0 behaves like SHAD with 0
- Negative values are undefined.
The 32-bit I-Forms will be organized into block-ranges.
- 0xx0, MOVI20
- 0xx1, MOVI20S
- 3xx1, MOV I-Forms
- 3xx9, Reserved/Unused
- 82xx, XPFX1
- / 83xx, XPFX3
- / 86xx, XPFX4
- / 87xx, XPFX5
- 8Axx, MOVI24
- 8Cxx, XPFX2
- 8Exx, XPFX0
- CCxx, XPFY0 (BJX1-64 Only)
- CDxx, XPFZ0 (BJX1-64 Only, 64-bit I-Form)
- CExx, XPFY1 (BJX1-64 Only)
- CFxx, XPFZ1 (BJX1-64 Only, 48-bit I-Form)
- FxxF, XPFV0 (FPU/SIMD)
Basic I-Forms (16-bit)
- 0---
- 0--0 RES (32-bit ops)
- 0--1 RES (32-bit ops)
- 0--2
- 0n02 STC./Q SR, Rn //Copy SR to Rn
- 0n12 STC./Q GBR, Rn //Copy GBR to Rn
- 0n22 STC./Q VBR, Rn //Copy VBR to Rn
- 0n32 STC./Q SSR, Rn //Copy SSR to Rn
- 0n42 STC./Q SPC, Rn //Copy SPC to Rn
- 0n52 -
- 0n62 -
- 0n72 ! STC./Q PC, Rn //Copy PC+4 to Rn
- 0nM2 STC./Q Rm_B, Rn //Copy Rm_B to Rn (Other Bank)
- 0--3
- 0m03 BSRF Rm //Branch to Subroutine (PC+Rm+4)
- 0-13 -
- 0m23 BRAF Rm //Branch to Label (PC+Rn+4)
- 0n33 -
- 0n43 -
- 0n53 -
- 0n63 -
- 0n73 -
- 0n83 PREF @Rn //Prefetch memory for address
- 0n93 -
- 0nA3 -
- 0nB3 -
- 0nC3 MOVCA.L R0, Rn
- 0nE3 ICBI @Rn //Invalidates I-Cache at Address
- 0nm4 MOV.B Rm, @(R0,Rn) //Move Byte Rm to R0+Rn
- 0nm5 MOV.W/Q Rm, @(R0,Rn) //Move Word Rm to R0+Rn
- 0nm6 MOV.L Rm, @(R0,Rn) //Move DWord Rm to R0+Rn
- 0nm7 MUL.L/Q Rm, Rn //Multiply Rm and Rn and store MACL
- 0--8 //Operations without arguments
- 0008 CLRT //Clear SR.T
- 0018 SETT //Set SR.T
- 0028 CLRMAC //Clear MACH and MACL
- 0038 LDTLB //LDTLB
- 0048 CLRS //Clear SR.S
- 0148 ICLRMD.DQ //Clear SR.DQ
- 0248 ICLRMD.JQ //Clear SR.JQ
- 0348 ICLRMD.JDQ //Clear SR.JQ and SR.DQ
- 0058 SETS //Set SR.S
- 0158 ISETMD.DQ //Set SR.DQ
- 0258 ISETMD.JQ //Set SR.JQ
- 0358 ISETMD.JQ //Set SR.JQ and SR.DQ
- 0068 NOTT
- 0x78 -
- 0x88 -
- 0x98 -
- 0xA8 -
- 0xB8 -
- 0xC8 -
- 0xD8 -
- 0xE8 -
- 0xF8 -
- 0--9
- 0i09 NOP //NOP
- 0019 DIV0U //Unsigned Divide
- 0n29 MOVT Rn //Copy T bit to Rn
- 0n39 MOVRT Rn
- 0x49 -
- 0x59 -
- 0x69 -
- 0x79 -
- 0x89 -
- 0x99 -
- 0mA9 MOVUA.L R0, @Rm //MOV Unaligned
- 0mE9 MOVUA.L R0, @-Rm //MOV Unaligned
- 0xF9 -
- 0--A
- 0n0A STS./Q MACH, Rn //Copy MACH to Rn
- 0n1A STS./Q MACL, Rn //Copy MACL to Rn
- 0n2A STS./Q PR, Rn //Copy PR to Rn
- 0n3A STC./Q SGR, Rn
- 0n4A -
- 0n5A STS./Q FPUL, Rn //Copy FPUL to Rn
- 0n6A STS./Q FPSCR, Rn //Copy FPSCR to Rn
- 0n7A -
- 0n8A -
- 0n9A -
- 0nAA -
- 0nBA -
- 0nCA -
- 0nDA -
- 0nEA -
- 0nFA STC./Q DBR, Rn //Copy DBR to Rn
- 0--B
- 000B RTS //Return from Function
- 001B SLEEP //Sleep until interrupt
- 002B RTE //Return From Exception
- 003B BRK //Breakpoint Exception
- 004B -
- 005B / RESBANK
- 006B RTS/N
- 0m7B ? RTV/N Rm
- 0x8B -
- 0x9B -
- 00AB / SYNCO //Delay until all preceding operations complete
- 0xBB -
- 0xCB -
- 0xDB -
- 0xEB -
- 0xFB -
- 0nmC MOV.B @(R0,Rm), Rn //Load Byte From R0+Rm into Rn
- 0nmD MOV.W/Q @(R0,Rm), Rn //Load Word/Quad From R0+Rm into Rn
- 0nmE MOV.L @(R0,Rm), Rn //Load DWord From R0+Rm into Rn
- 0nmF MAC.L @Rm+, @Rn+ //Load/Mul Rm and Rn and add to MACH/MACL
- ( Deprecated for BJX1 )
- 1nmd MOV.L Rm, @(Rn,disp) //Store DWord Rm to Rn+4*Disp
- 2---
- 2nm0 MOV.B Rm, @Rn //Store Byte Rm to @Rn
- 2nm1 MOV.W/Q Rm, @Rn //Store Word/Quad Rm to @Rn
- 2nm2 MOV.L Rm, @Rn //Store Rm to @Rn
- 2nm3 CAS.L Rm, Rn, @R0 //Compare and Exchange
- 2nm4 MOV.B Rm, @-Rn //Store Rm to Byte @Rn then Rn=Rn-1
- 2nm5 MOV.W/Q Rm, @-Rn //Store Rm to Word/Quad @Rn then Rn=Rn-2|8
- 2nm6 MOV.L Rm, @-Rn //Store Rm to DWord @Rn then Rn=Rn-4
- 2nm7 DIV0S Rm, Rn //Setup for signed division
- 2nm8 TST./Q Rm, Rn //Test Rm&Rn, updating SR.T
- 2nm9 AND./Q Rm, Rn //And Rm and Rn, Storing result in Rn
- 2nmA XOR./Q Rm, Rn //Xor Rm and Rn, Storing result in Rn
- 2nmB OR./Q Rm, Rn //Or Rm and Rn, Storing result in Rn
- 2nmC CMPSTR Rm, Rn //Compare Rm and Rn for matching bytes
- 2nmD XTRCT Rm, Rn //Low bits from Rm and High bits from Rn
- 2nmE MULU.W/Q Rm, Rn //Multiply Unsigned Word/DWord, Dst=MACL
- DQ=1: 64x64 -> 128-bit, Result in XMACH:MACH:XMACL:MACL
- 2nmF MULS.W/Q Rm, Rn //Multiply Signed Word/DWord, Dst=MACL
- DQ=1: 64x64 -> 128-bit Result in XMACH:MACH:XMACL:MACL
- 3---
- 3nm0 CMPEQ./Q Rm, Rn //Compare for Equality
- 3--1 RES (32-bit ops)
- 3nm2 CMPHS./Q Rm, Rn //Compare for unsigned Greater/Equal
- 3nm3 CMPGE./Q Rm, Rn //Compare for signed Greater/Equal
- 3nm4 DIV1 Rm, Rn //Inner part of divide
- 3nm5 DMULU.L Rm, Rn //Unsigned Multiply, result in MACH:MACL
- 3nm6 CMPHI./Q Rm, Rn //Compare for unsigned Greater
- 3nm7 CMPGT./Q Rm, Rn //Compare for signed Greater
- 3nm8 SUB./Q Rm, Rn //Subtract
- 3--9 RES (32-bit ops)
- 3nmA SUBC./Q Rm, Rn //Subtract, Carry -> T
- 3nmB SUBV./Q Rm, Rn //Subtract, Overflow -> T
- 3nmC ADD./Q Rm, Rn //Add
- 3nmD DMULS.L Rm, Rn //Signed Multiply, result in MACH:MACL
- 3nmE ADDC./Q Rm, Rn //Add with Carry, Carry -> T
- 3nmF ADDV./Q Rm, Rn //Add, Overflow -> T
- 4---
- 4--0
- 4n00 SHLL./Q Rn
- 4n10 DT./Q Rn
- 4n20 SHAL./Q Rn
- 4n80 -
- 4mF0 -
- 4--1
- 4n01 SHLR./Q Rn
- 4n11 CMPPZ./Q Rn
- 4n21 SHAR./Q Rn
- ..
- 4n61 ? SHTF16 FPUL, Rn
- 4m71 ? LDHF16 Rm, FPUL
- 4n81 -
- 4n91 -
- 4nA1 ! MOV.Q Rm, @(PC, R0)
- 4nB1 ! FMOV.S FRm, @(PC, R0)
- 4mC1 ! MOV.B Rm, @(PC, R0)
- 4mD1 ! MOV.W/Q Rm, @(PC, R0)
- 4mE1 ! MOV.L Rm, @(PC, R0)
- 4mF1 -
- 4--2
- 4n02 STS.L/Q MACH, @-Rn
- 4n12 STS.L/Q MACL, @-Rn
- 4n22 STS.L/Q PR, @-Rn
- 4n32 STC.L/Q SGR, @-Rn
- 4n42 -
- 4n52 STS.L/Q FPUL, @-Rn
- 4n62 STS.L/Q FPSCR, @-Rn
- 4-72 -
- ..
- 4n62 STS.L/Q DBR, @-Rn
- 4--3
- 4n03 STC.L/Q SR, @-Rn
- 4n13 STC.L/Q GBR, @-Rn
- 4n23 STC.L/Q VBR, @-Rn
- 4n33 STC.L/Q SSR, @-Rn
- 4n43 STC.L/Q SPC, @-Rn
- 4n53 -
- 4n63 -
- 4n73 ! STC.L/Q PC, @-Rn //Store PC+4 to memory
- 4nM3 STC.L/Q Rm_B, @-Rn
- 4--4
- 4n04 ROTL./Q Rn
- 4n14 ! ROT32 Rn //Rn<->RHn
- 4-24 ROTCL./Q Rn
- 4n34 ! SHLL4 Rn //(Rn<<4)->Rn
- 4n44 EXTU.L Rn //zero extend 32 -> 64
- 4n54 EXTS.L Rn //sign extend 32 -> 64
- 4n64 MOV.Q/W @R0, Rn //(Alt MOV.W, BJX1-64)
- 4m74 MOV.Q/W Rm, @R0 //(Alt MOV.W, BJX1-64)
- 4n84 / DIVU R0, Rn
- 4n94 / DIVS R0, Rn
- ..
- 4-F4
- 4nF4 -
- 4--5
- 4n05 ROTR./Q Rn //Rotate Right
- 4n15 CMPPL./Q Rn //Compare Rn>0
- 4n25 ROTCR./Q Rn
- 4n35 ! SHLR4 Rn //(Rn>>4)->Rn
- 4n45 ! MOVHI R0, RHn //R0->RHn
- 4m55 ! MOVHI RHm, R0 //RHm->R0
- 4n65 -
- 4n75 -
- 4n85 -
- 4n95 -
- 4nA5 ! MOV.Q @(PC, R0), Rn
- 4nB5 ! FMOV.S @(PC, R0), FRn
- 4nC5 ! MOV.B @(PC, R0), Rn
- 4nD5 ! MOV.W/Q @(PC, R0), Rn
- 4nE5 ! MOV.L @(PC, R0), Rn
- 4nF5 ! LEA.B @(PC, R0), Rn
- 4--6
- 4m06 LDS.L/Q @Rm+, MACH
- 4m16 LDS.L/Q @Rm+, MACL
- 4m26 LDS.L/Q @Rm+, PR
- 4m36 LDC.L/Q @Rm+, SGR
- 4m46 -
- 4m56 LDS.L/Q @Rm+, FPUL
- 4m66 LDS.L/Q @Rm+, FPSCR
- 4-76 -
- ..
- 4-F6 LDC.L/Q @Rm+, DBR
- 4--7
- 4m07 LDC.L/Q @Rm+, SR
- 4m17 LDC.L/Q @Rm+, GBR
- 4m27 LDC.L/Q @Rm+, VBR
- 4m37 LDC.L/Q @Rm+, SSR
- 4m47 LDC.L/Q @Rm+, SPC
- 4m57 -
- 4-67 -
- 4m77 ! LDC.L/Q @Rm+, PC //? Load Delay Branch
- 4mN7 LDC.L/Q @Rm+, Rm_B
- 4--8
- 4n08 SHLL2./Q Rn
- 4n18 SHLL8./Q Rn
- 4n28 SHLL16./Q Rn
- 4n38 ! SHLL32 Rn //Rn->RHn, 0->Rn
- 4m48 ! PUSH.L/Q Rm //MOV.L/Q Rm, @-R15
- 4n58 ! POP.L/Q Rn //MOV.L/Q @R15+, Rn
- 4m68 ! PUSH2.L/Q Rm //PUSH R16..R31 (BJX1-64)
- 4n78 ! POP2.L/Q Rn //POP R16..R31 (BJX1-64)
- 4-88 -
- ...
- 4-F8 -
- 4--9
- 4n09 SHLR2./Q Rn
- 4n19 SHLR8./Q Rn
- 4n29 SHLR16./Q Rn
- 4n39 ! SHLR32 Rn //RHn->Rn, 0->RHn
- 4mA9 MOVUA.L @Rm, R0 //MOV Unaligned
- 4mE9 MOVUA.L @Rm+, R0 //MOV Unaligned
- 4--A
- 4m0A LDS./Q Rm, MACH
- 4m1A LDS./Q Rm, MACL
- 4m2A LDS./Q Rm, PR
- 4m3A LDC./Q Rm, SGR
- 4m4A -
- 4m5A LDS./Q Rm, FPUL
- 4m6A LDS./Q Rm, FPSCR
- 4-7A -
- ..
- 4-EA -
- 4mFA LDS./Q Rm, DBR
- 4--B
- 4m0B JSR Rm
- 4m1B TAS.B Rm
- 4m2B JMP Rm
- ..
- 4m4B / JSR/N
- ..
- 4m8B MOV.B R0, @Rn+
- 4m9B MOV.W/Q R0, @Rn+
- 4mAB MOV.L R0, @Rn+
- 4-BB -
- 4mCB MOV.B @-Rm, R0
- 4mDB MOV.W/Q @-Rm, R0
- 4mEB MOV.L @-Rm, R0
- 4-FB -
- 4nmC SHAD./Q Rm, Rn
- 4nmD SHLD./Q Rm, Rn
- 4--E
- 4m0E LDC./Q Rm, SR
- 4m1E LDC./Q Rm, GBR
- 4m2E LDC./Q Rm, VBR
- 4m3E LDC./Q Rm, SSR
- 4m4E LDC./Q Rm, SPC
- 4m5E -
- 4m6E -
- 4m7E ! LDC./Q Rm, PC //UB
- 4mNE LDC./Q Rm, Rm_B
- 4nmF MAC.W/Q @Rm+, @Rn+
- ( Deprecated for BJX1 )
- 4--0
- 5nmd MOV.L @(Rm,disp), Rn
- 6---
- 6nm0 MOV.B @Rm, Rn //Load Byte
- 6nm1 MOV.W/Q @Rm, Rn //Load Word or Quad
- 6nm2 MOV.L @Rm, Rn //Load DWord
- 6nm3 MOV./Q Rm, Rn //MOV Registers
- 6nm4 MOV.B @Rm+, Rn //Load Byte with post-increment
- 6nm5 MOV.W/Q @Rm+, Rn //Load Word or Quad with post-increment
- 6nm6 MOV.L @Rm+, Rn //Loag DWord with post increment
- 6nm7 NOT./Q Rm, Rn //Bitwise Not
- 6nm8 SWAP.B Rm, Rn //Swap Low/High bits per Byte
- 6nm9 SWAP.W Rm, Rn //Swap Low/High bits per Word
- 6nmA NEGC./Q Rm, Rn //Negate with carry
- 6nmB NEG./Q Rm, Rn //Negate
- 6nmC EXTU.B Rm, Rn //Zero Extend Byte
- 6nmD EXTU.W Rm, Rn //Zero Extend Word
- 6nmE EXTS.B Rm, Rn //Sign Extend Byte
- 6nmF EXTS.W Rm, Rn //Sign Extend Word
- 7nii ADD./Q #imm, Rn //Add immediate to register
- 8---
- 80nd MOV.B R0, @(Rn,disp) //Store Byte
- 81nd MOV.W/Q R0, @(Rn,disp) //Store Word or Quad
- Always Word if disp==0
- 82-- - XPFX1/Escape32B
- 83dd / JSR/N disp
- 83pd ! MOV.L Rm, @(SP,disp4) //R8..R14,R0; Disp=16..31
- 83Qd ! MOV.L @(SP,disp4), Rn //R8..R14,R0; Disp=16..31
- 84md MOV.B @(Rm,disp), R0
- 85md MOV.W/Q @(Rm,disp), R0
- Always Word if disp==0
- 86-- / BST / BCLR
- 87-- / BST / BCLR
- 86pd ! FMOV.S FRm, @(SP,disp4) //FR8..R15; Disp=0..15
- 86Qd ! FMOV.S @(SP,disp4), FRn //FR8..R15; Disp=0..15
- 87pd ! FMOV.S FRm, @(SP,disp4) //FR8..R15; Disp=16..31 (BJX1-32)
- 87Qd ! FMOV.S @(SP,disp4), FRn //FR8..R15; Disp=16..31 (BJX1-32)
- 87pd / MOV.Q Rm, @(SP,disp4) //R8..R14,R0; Disp=0..15 (BJX1-64)
- 87Qd / MOV.Q @(SP,disp4), Rn //R8..R14,R0; Disp=0..15 (BJX1-64)
- 88ii CMPEQ./Q #imm, R0
- 89dd BT label
- 8Aii-iiii MOVI24 #imm24, R0 //32-bit op, loads 24-bit immediate.
- 8Bdd BF label
- 8Cii XPFX2
- 8C0x..8C7x xxxx //32-bit I-Forms
- 8C8x..8CFx xxxx //64-bit I-Forms (Resv)
- 8Ddd BTS label
- 8Eii XPFX0/Escape32 //Escape for 32 bit I-Forms
- Combines with a following instruction to form a new one.
- 8Fdd BFS label
- 9ndd MOV.W/Q @(PC,disp), Rn
- DQ=0: Load WORD from PC+4+disp*2
- DQ=1: Load QWORD from PC+4+disp*8 (DWORD Aligned)
- Addd BRA label
- Bddd BSR label
- C---
- C0dd MOV.B R0, @(GBR,disp) //32-bit only
- C0md MOV.Q Rm, @(SP,disp4) //BJX1-64
- C1dd MOV.W R0, @(GBR,disp) //32-bit only
- C1PQ
- C1qp MOV.Q Rm, @Rn
- C1qP MOV.Q @Rm, Rn
- C1Qp MOV.Q Rm, @(Rn, R0)
- C1QP MOV.Q @(Rm, R0), Rn
- C2dd MOV.L R0, @(GBR,disp) //32-bit only
- C3jj TRAPA #imm
- C4dd MOV.B @(GBR,disp), R0 //32-bit only
- C4md MOV.Q @(SP,disp4), Rn //BJX1-64
- C5dd MOV.W @(GBR,disp), R0 //32-bit only
- C5PQ
- C5qp CMPQEQ Rm, Rn
- C5qP TSTQ Rm, Rn
- C5Qp CMPQHI Rm, Rn
- C5QP CMPQGT Rm, Rn
- C6dd MOV.L @(GBR,disp), R0 //32-bit only
- C7dd MOVA @(PC,disp), R0 //Load Address into R0, DWORD aligned.
- C8jj TST./Q #imm, R0
- C9jj AND./Q #imm, R0
- CAjj XOR./Q #imm, R0
- CBjj OR./Q #imm, R0
- CCjj TST.B #imm, @(GBR,R0) //32-bit only, BJX1 deprecated
- CCxx-xxxx //BJX1-64
- CDjj AND.B #imm, @(GBR,R0) //32-bit only, BJX1 deprecated
- CDxx-xxxx //BJX1-64
- CEjj XOR.B #imm, @(GBR,R0) //32-bit only, BJX1 deprecated
- CExx-xxxx-xxxx-xxxx ? //BJX1-64
- CFjj OR.B #imm, @(GBR,R0) //32-bit only, BJX1 deprecated
- CFxx-xxxx-xxxx ? //BJX1-64
- C0dd MOV.B R0, @(GBR,disp) //32-bit only
- Dndd MOV.L @(PC,disp), Rn //Load DWord, DWord aligned.
- DQ=1: Result extended to QWord
- Enii MOV./Q #imm, Rn //Load immediate into register.
- Fxxx: FPU/SIMD Block
For full FPU, see NVSIMD Spec.
- A core may opt to instead provide a more basic FPU.
- Basic FPU will only provide for scalar operation.
- Or, none at all.
- ! will denote patterns that are in-use but unavailable in Basic FPU.
- FPU Registers are 32-bit and hold single or split-double values
- The FPUSCR.SZ bit controls whether to copy a single or register pair.
- The FPUSCR.PR bit selects between Single and Split-Double calculations.
- NV SIMD Spec covers the Full FPU
- 64-bit operation will be basically the same as 32-bit operation.
- The FPU is basically a superset of the traditional FPU.
- F---
- Fnm0 FADD FRm, FRn
- Fnm1 FSUB FRm, FRn
- Fnm2 FMUL FRm, FRn
- Fnm3 FDIV FRm, FRn
- Fnm4 FCMPEQ FRm, FRn
- Fnm5 FCMPGT FRm, FRn
- Fnm6 FMOV.S @(R0,Rm), FRn
- Fnm7 FMOV.S FRm, @(R0,Rn)
- Fnm8 FMOV.S @Rm, FRn
- Fnm9 FMOV.S @Rm+, FRn
- FnmA FMOV.S FRm, @Rn
- FnmB FMOV.S FRm, @-Rn
- FnmC FMOV FRm, FRn
- F--D
- Fn0D FSTS FRn
- Fm1D FLDS FRm
- Fn2D FLOAT FRn
- Fm3D FTRC FRm
- Fn4D FNEG FRn
- Fn5D FABS FRn
- Fn6D FSQRT FRn
- F-7D !
- Fn8D FLDI0 FRn //Load 0.0
- Fn9D FLDI1 FRn //Load 1.0
- FnAD FCNVSD FRn
- FnBD FCNVDS FRm
- F-CD !
- FiDD PSETMD #imm4
- F-ED !
- F-FD
- F0FD !
- F1FD !
- F2FD !
- F3FD FSCHG //Flips FPSCR.SZ
- F4FD !
- F5FD !
- F6FD !
- F7FD FPCHG //Flips FPSCR.PR
- F8FD !
- F9FD !
- FAFD !
- FBFD FRCHG //Flips FPSCR.FR
- FCFD !
- FDFD !
- FEFD !
- FnmE FMAC FRm, FRn
- F--F ! (BT Reserved-32)
- (PR=0, SZ=0): Arithmetic operators operate on Float, FMOV.S is also Float.
- (PR=1, SZ=0): Arithmetic operators operate on Double, FMOV.S is still Float.
- (PR=0, SZ=1): Arithmetic operators will operate on Float, FMOV.S is Pair.
- Copies a pair of floats, which are reversed on Little-Endian targets.
- (PR=1, SZ=1): BJX1, both arithmetic and FMOV.S will operate on Double.
- In BJX1, this will put the two halves in the correct order.
- When 0, Banks A and B will be in their normal order.
- When 1, Banks A and B will be swapped.
- This swaps FRn and XFn for Float operations.
- This swaps Even/Odd doubles for Double operation.
- imm4=zpmm
- z: FPSCR.SZ
- p: FPSCR.PR
- mm: Rounding Mode
- Other bits for FPSCR are left as-is.
- Float operations will operate of FR0..FR15.
- FPSCR.FR will allow alternating between FR0..FR15 and XF0..XF15.
- Double operations will operate on Pairs.
- Even=(FR1, FR0), (FR3, FR2), ...
- Odd=(XF1, XF0), (XF3, XF2), ...
- In BJX1, there will be 16 logical double registers.
- In legacy operation, only the 8 even doubles are accessible.
- 8Evo-Fnm6 FMOV.S @(Rm,Ro), FRn
- 8Evo-Fnm7 FMOV.S FRm, @(Rn,Ro)
- 8Evd-Fnm8 FMOV.S @(Rm,disp4), FRn
- 8Ev0-Fnm9 FMOV.S @Rm+, FRn
- 8Evd-FnmA FMOV.S FRm, @(Rn,disp4)
- 8Ev0-FnmB FMOV.S FRm, @-Rn
- 8Evv-FnmC FMOV FRm, FRn //S: FPU MOV
- 8Eii-FiDD PSETMD #imm12 //Packed Set Mode (Ext/Resv)
- wwww-xxyy
- wwww:
- 0000: FRm, FRn //Copy FRn
- 0001:
- 0010:
- 0011: Rm, FRn //Copy GPR to FRn (FMOV.IS)
- 0100:
- 0101: DRm, DRn //Copy DRn
- 0110:
- 0111: Rm, DRn //Copy GPR to DRn
- 1000: Rm, Rn //Copy GPR (MOV.L)
- 1001:
- 1010: Rm, Rn //Copy GPR (MOV.Q)
- 1011:
- 1100: FRm, Rn //Copy FRm to GPR (FMOV.SI)
- 1101: DRm, Rn //Copy DRm to GPR (Rn, RnH)
- 1110:
- 1111: ! XRm, XRn
- xx: Bit4/5 of Rn
- yy: Bit4/5 of Rm
- wwxy
- ww=00: FRn
- ww=01: DRn
- Loads (FRn+0,FRn+1)
- ww=10: DRn
- Loads value in correct ordering for Double
- ww=11: ! XRn
- imm12=000v-wwfz-pdmm
- v: ! VE
- Reserved (Set to 0) in Basic FPU.
- ww: ! Swap Mode
- Reserved (Set to 0) in Basic FPU.
- f: FR
- z: SZ
- p: PR
- d: DN
- mm: Rounding Mode
- Other bits for FPSCR are cleared to 0.
32-bit I-Forms (currently unsupported, reserved):
- 0ni0-iiii MOVI20 #imm, Rn
- 0ni1-iiii MOVI20S #imm, Rn
- 3nm1-0ddd MOV.B Rm, @(Rn, disp)
- 3nm1-1ddd MOV.W Rm, @(Rn, disp)
- 3nm1-2ddd MOV.L Rm, @(Rn, disp)
- 3nm1-3ddd FMOV.S FRm, @(Rn, disp)
- 3nm1-4ddd MOV.B @(Rm, disp), Rn
- 3nm1-5ddd MOV.W @(Rm, disp), Rn
- 3nm1-6ddd MOV.L @(Rm, disp), Rn
- 3nm1-7ddd FMOV.S @(Rm, disp), FRn
- 3nm1-8ddd MOVU.B @(Rm, disp), Rn
- 3nm1-9ddd MOVU.W @(Rm, disp), Rn
- 3ni9-Xddd !
- This group of instructions is not present in BJX1.
For XPFX0 I-Forms
- The prefix will give the high bits of multi-part immediates for 32-bit I-Forms.
- 8E12 EC34: MOV 0x1234, R12
- The endianess of each instruction WORD will depend on the target.
- 0---
- 8Eoo-0oo0 (Resv)
- 8Eoo-0oo1 (Resv)
- 8Eoo-0oo2 (Resv)
- 8Eoo-0oo3 (Resv)
- 8Eod-0nm4 MOV.B Rm, @(Rn,Ro,disp4) //Move Byte Rm to Rn+(Ro+disp)
- 8Eod-0nm5 MOV.W Rm, @(Rn,Ro,disp4) //Move Word Rm to Rn+(Ro+disp)*2
- 8Eod-0nm6 MOV.L Rm, @(Rn,Ro,disp4) //Rn+(Ro+disp)*4
- 8Eod-0nm7 MOV.Q Rm, @(Rn,Ro,disp4) //Rn+(Ro+disp)*8
- 8Eoo-0oo8 (Resv Ext No-Arg Ops)
- 8Eno-0oo9 (Resv Ext Unary Ops)
- 8Enm-0ooA Resv
- 8Enm-0ooB (Resv Ext Binary Ops)
- 8Eod-0nmC MOV.B @(Rm,Ro,disp4), Rn //Load Byte At Rm+Ro+disp into Rn
- 8Eod-0nmD MOV.W @(Rm,Ro,disp4), Rn //Load Word At Rm+(Ro+disp)*2 into Rn
- 8Eod-0nmE MOV.L @(Rm,Ro,disp4), Rn //Load DWord
- 8Eod-0nmF MOV.Q @(Rm,Ro,disp4), Rn //Load QWord
- 8Edd-1nmo MOV.L Rm, @(Rn,Ro,disp8s) //Rn+4*(Ro+Disp)
- 2---
- 8Edd-2nm0 MOV.B Rm, @(Rn,disp8s) //Store Byte Rm to @Rn
- 8Edd-2nm1 MOV.W Rm, @(Rn,disp8s) //Store Word Rm to @Rn
- 8Edd-2nm2 MOV.L Rm, @(Rn,disp8s) //Store DWord
- 8Edd-2nm3 MOV.Q Rm, @(Rn,disp8s) //Store QWord
- 8Edd-2nm4 FMOV.S FRm, @(Rn,disp8s) //Store Float
- 8Edd-2nm5 -
- 8Edd-2nm6 FMOV.S @(Rm,disp8s), FRn //Load Float
- 8Edd-2nm7 -
- 8Edd-2nm8 -
- 8Ejj-2nm9 AND Rm, #imm8, Rn //Rn=Rm&Imm8
- 8Ejj-2nmA XOR Rm, #imm8, Rn //
- 8Ejj-2nmB OR Rm, #imm8, Rn //
- 8Eeo-2nmC -
- 8Eeo-2nmD -
- 8Ejj-2nmE MULL Rm, #imm8, Rn //Rn=Rm*Imm8 (Imm8 Zero-Ext)
- 8Ejj-2nmF MULL Rm, #-imm8, Rn //Rn=Rm*Imm8 (Imm8 One-Ext)
- 3---
- 8Eii-3ni0 CMPEQ./Q #imm12, Rn //Compare for unsigned Greater/Equal
- 8Exx-3xx1 -
- 8Eii-3ni2 CMPHS./Q #imm12, Rn //Compare for unsigned Greater/Equal
- 8Eii-3ni3 CMPGE./Q #imm12, Rn //Compare for signed Greater/Equal
- 8Ejj-3nk4 ? LDSH8R #imm8r, Rn //TBD, Load Shift/Rotate (Pad 0s)
- 8Ejj-3nk5 ? LDSH8N #imm8n, Rn //TBD, Load Shift/Rotate (Pad 1s)
- 8Eii-3ni6 CMPHI./Q #imm12, Rn //Compare for unsigned Greater
- 8Eii-3ni7 CMPGT./Q #imm12, Rn //Compare for signed Greater
- 8Ejj-3nm8 SUB Rm, #imm8, Rn //Rn=Rm-Imm8
- 8Ejj-3nm9 AND Rm, #-imm8, Rn //Rn=Rm&Imm8
- 8Edd-3nmA -
- 8Edd-3nmB -
- 8Ejj-3nmC ADD Rm, #imm8, Rn //Rn=Rm+Imm8
- 8Edd-3nmD -
- 8Edd-3nmE -
- 8Edd-3nmF -
- 4---
- 8Exx-4xx0 -
- 8Exx-4xx1 -
- 8Exx-4xx2 -
- 8Est-4nb3 TACB2
- 8Est-4n03 ADD Rs, Rt, Rn // Rn=Rs+Rt
- 8Est-4n13 SUB Rs, Rt, Rn // Rn=Rs-Rt
- 8Est-4n23 MUL Rs, Rt, Rn // Rn=Rs*Rt
- 8Est-4n33 AND Rs, Rt, Rn // Rn=Rs&Rt
- 8Est-4n43 OR Rs, Rt, Rn // Rn=Rs|Rt
- 8Est-4n53 XOR Rs, Rt, Rn // Rn=Rs^Rt
- 8Est-4n63 SHLD./Q Rs, Rt, Rn // Rn=Rs SHLD Rt
- 8Est-4n73 SHLR./Q Rs, Rt, Rn // Rn=Rs SHLD -Rt
- 8Est-4n83 SHAD./Q Rs, Rt, Rn // Rn=Rs SHAD Rt
- 8Est-4n93 SHAR./Q Rs, Rt, Rn // Rn=Rs SHAD -Rt
- 8Est-4nA3 -
- 8Est-4nB3 -
- 8Est-4nC3 FADD FRs, FRt, FRn // FRn=FRs+FRt
- 8Est-4nD3 FSUB FRs, FRt, FRn // FRn=FRs-FRt
- 8Est-4nE3 FMUL FRs, FRt, FRn // FRn=FRs*FRt
- 8Est-4nF3 FDIV FRs, FRt, FRn // FRn=FRs/FRt
- 8Exx-4xx4
- 8Eii-4n84 ?/ MOV.B #imm, @Rn //Store Imm to memory
- 8Eii-4n94 ?/ MOV.W #imm, @Rn //
- 8Eii-4nA4 ?/ MOV.L #imm, @Rn //
- 8Eii-4nB4 ?/ MOV.Q #imm, @Rn //
- 8Eii-4nC4 ?/ MOV.B #imm, @-Rn //Store Imm to memory (Dec)
- 8Eii-4nD4 ?/ MOV.W #imm, @-Rn //
- 8Eii-4nE4 ?/ MOV.L #imm, @-Rn //
- 8Eii-4nF4 ?/ MOV.Q #imm, @-Rn //
- 8Edd-4mb5 ? BRxx Rm, disp8
- b=0, BREQ (Rm==0)
- b=1, BRNE (Rm!=0)
- b=2: BRGT (Rm> 0)
- b=3: BRLE (Rm<=0)
- b=4: BRGE (Rm>=0)
- b=5: BRLT (Rm< 0)
- b=6: BRHI (Rm> 0, Unsigned)
- b=7: BRBE (Rm<=0, Unsigned)
- 8Edd-4ST6 ? BRxx Rs, Rt, disp8
- 8Edd-4ST7 ? BRxx Rs, Rt, disp8
- 0100-bsss-bttt-011b //Rs/Rt=R8..R14
- b=000: BREQ
- b=001: BRNE
- b=010: BRGT
- b=011: BRLE
- b=100: BRGE
- b=101: BRLT
- b=110: -
- b=111: -
- 8Exx-4xx8 -
- 8Exx-4xx9 -
- 8Exx-4xxA -
- 8Exx-4xxB -
- 8Eii-4nmC SHAD./Q Rm, #imm, Rn //Rn=Rm SAL Imm8 | Rn=Rm SAR Imm8
- 8Eii-4nmD SHLD./Q Rm, #imm, Rn //Rn=Rm SHL Imm8 | Rn=Rm SHR Imm8
- 8Exx-4xxE -
- 8Emo-4n0E MOVU.B @(Rm,Ro), Rn
- 8Emo-4n1E MOVU.W @(Rm,Ro), Rn
- 8Emo-4n2E FMOV.S @(Rm,Ro), FRn
- 8Emo-4n3E FMOV.S FRm, @(Rn,Ro)
- 8Emo-4n4E MOV.B Rm, @(Rn,Ro)
- 8Emo-4n5E MOV.W Rm, @(Rn,Ro)
- 8Emo-4n6E MOV.L Rm, @(Rn,Ro)
- 8Emo-4n7E MOV.Q Rm, @(Rn,Ro)
- 8Emo-4n8E LEA.B @(Rm,Ro), Rn //LEA Byte
- 8Emo-4n9E LEA.W @(Rm,Ro), Rn //LEA Word
- 8Emo-4nAE LEA.L @(Rm,Ro), Rn //LEA DWord
- 8Emo-4nBE LEA.Q @(Rm,Ro), Rn //LEA QWord
- 8Emo-4nCE MOV.B @(Rm,Ro), Rn
- 8Emo-4nDE MOV.W @(Rm,Ro), Rn
- 8Emo-4nEE MOV.L @(Rm,Ro), Rn
- 8Emo-4nFE MOV.Q @(Rm,Ro), Rn
- 8Exx-4xxF -
- 8Edd-5nmo MOV.L @(Rm,Ro,disp), Rn //Rm+(Ro+disp)*4
- 6---
- 8Edd-6nm0 MOV.B @(Rm,disp8s), Rn
- 8Edd-6nm1 MOV.W @(Rm,disp8s), Rn
- 8Edd-6nm2 MOV.L @(Rm,disp8s), Rn
- 8Edd-6nm3 MOV.Q @(Rm,disp8s), Rn
- 8Eod-6nm4 LEA.B @(Rm,Ro,disp4), Rn //Load Byte At Rm+Ro+disp into Rn
- 8Eod-6nm5 LEA.W @(Rm,Ro,disp4), Rn //Load Word At Rm+(Ro+disp)*2 into Rn
- 8Eod-6nm6 LEA.L @(Rm,Ro,disp4), Rn //Load DWord
- 8Eod-6nm7 LEA.Q @(Rm,Ro,disp4), Rn //Load QWord
- 8Edd-6nm8 LEA.B @(Rm,disp8s), Rn //Rn=Rm+disp*1
- 8Edd-6nm9 LEA.W @(Rm,disp8s), Rn //Rn=Rm+disp*2
- 8Edd-6nmA LEA.L @(Rm,disp8s), Rn //Rn=Rm+disp*4
- 8Edd-6nmB LEA.Q @(Rm,disp8s), Rn //Rn=Rm+disp*8
- 8Edd-6nmC MOVU.B @(Rm,disp8s), Rn //Rm+disp*1
- 8Edd-6nmD MOVU.W @(Rm,disp8s), Rn //Rm+disp*2
- 8Edd-6nmE MOVU.L @(Rm,disp8s), Rn //Rm+disp*4
- 8Edd-6nmF -
- 8Eii-7nii ADD./Q #imm16, Rn
- 8---
- 8Edd-80mo -
- 8Edd-81mo -
- 8Edd-82dd BRA/N disp16 //BRA, No Delay Slot
- 8Edd-83dd BSR/N disp16 //BSR, No Delay Slot
- 8Edd-84mo -
- 8Edd-85mo -
- 8Edd-86mo -
- 8Edd-87mo -
- 8Eii-88ii CMPEQ #imm16, R0
- 8Edd-89dd BT disp16
- 8Eii-8Aii LDHF16 #imm, FPUL //Load Half Imm16 into FPUL Float
- 8Edd-8Bdd BF disp16
- 8Eii-8Cii LDIF16 #imm, FPUL //Load (Imm16<<16) into FPUL
- 8Edd-8Ddd BTS disp16
- 8Exx-8Exx -
- 8Edd-8Fdd BFS disp16
- 8Eii-9nii LDSH16 #imm16, Rn //Rn=(Rn<<16)+Imm16
- 8Edd-Addd ? BRA disp20
- 8Edd-Bddd ? BSR disp20
- C---
- 8Edd-C0md MOV.B Rm, @(GBR,disp) //
- 8Edd-C1md MOV.W/Q Rm, @(GBR,disp) //
- 8Edd-C2md MOV.L Rm, @(GBR,disp) //
- 8Exx-C3xx -
- 8Edd-C4nd MOV.B @(GBR,disp), Rn //
- 8Edd-C5nd MOV.W/Q @(GBR,disp), Rn //
- 8Edd-C6nd MOV.L @(GBR,disp), Rn //
- 8Exx-C7xx -
- 8Eii-C8nj TST #imm12, Rn
- 8Eii-C9nj AND #imm12, Rn
- 8Ejj-CAnj XOR #imm12, Rn
- 8Ejj-CBnj OR #imm12, Rn
- 8Ejj-CCnk ? TST #imm8r, Rn //TBD
- 8Ejj-CDnk ? AND #imm8r, Rn //TBD
- 8Ejj-CEnk ? XOR #imm8r, Rn //TBD
- 8Ejj-CFnk ? OR #imm8r, Rn //TBD
- 8Eed-Dndd / (Drop)
- 8Eii-Enii MOV./Q #imm16, Rn
- 8Exx-Fxxx (Ext-FPU / SIMD)
- 8C0x-xxxx -
- 8C1x-xxxx -
- 8C2x-xxxx -
- 8C3x-xxxx -
- 8C4x-xxxx -
- 8C5x-xxxx -
- 8C6x-xxxx -
- 8C7x-xxxx -
These blocks only exists in BJX1-64A Profile.
- CC0e-xxxx XPFY0 OPREX
- CC1x-xxxx -
- CC2x-xxxx -
- CC3e-bnst XPFY0 TACB
- CC4x-xxxx -
- CC5x-xxxx -
- CC6x-xxxx -
- CC7x-xxxx -
XPFY0
- CC0e-xxxx: OPREX Prefix
- Extends arithmetic operators with an explicit size and extended registers.
- e: QNMB
- Q: 0=Single/DWORD (.L or .S), 1=Double/QWORD (.Q or .D)
- Arithmetic operations here will typically have an explicit size.
- Will select between MOV.L/MOV.Q forms for MOV.L/Q.
- For most ops, the high-order bits are preserved.
- N: Bit 4 for Rn
- M: Bit 4 for Rm
- GPR: Selects Rn/RHn
- FPR: Selects FRn/XFn
- B: Bank/Ro/...
- Bit 4 for Ro (if present)
- If no Ro or disp5 exists (GPR):
- MOV.B: Zero extend result (to DWord or QWord).
- MOV.W: Zero extend result (to DWord or QWord).
- MOV.L/Q: (Q,B)
- (0,0): MOV.L, Load DWord, Sign Extend
- (0,1): MOVU.L, Load DWord, Zero Extend to QWord
- (1,0): MOV.Q, Load QWord
- (1,1): Reserved
- EXTU.W / EXTS.W (Q,B)
- FPR: Reserved
- 0---
- CC0e-0nm0 -
- CC0e-0nm1 -
- CC0e-0nm2 (STC Block)
- CC0e-0nm3 -
- CC0e-0nm4 MOV.B Rm, @(R0,Rn) //Move Byte Rm to R0+Rn
- CC0e-0nm5 MOV.W Rm, @(R0,Rn) //Move Word Rm to R0+Rn
- CC0e-0nm6 MOV.L/Q Rm, @(R0,Rn) //Move DWord Rm to R0+Rn
- CC0e-0nm7 -
- CC0e-0nm8 -
- CC0e-0nm9 -
- CC0e-0nmA (STS Block)
- CC0e-0nmB -
- CC0e-0nmC MOV.B @(R0,Rm), Rn //Load Byte From R0+Rm into Rn
- CC0e-0nmD MOV.W @(R0,Rm), Rn //Load Word/Quad From R0+Rm into Rn
- CC0e-0nmE MOV.L/Q @(R0,Rm), Rn //Load DWord From R0+Rm into Rn
- CC0e-0nmF -
- 1---
- CC0e-1nmd ? MOV.L/Q Rm, @(Rn,disp5) //Store DWord Rm to Rn+(4|8)*Disp
- Deprecate?: Redundant with CExx-2nm2/2nm3
- 2---
- CC0e-2nm0 MOV.B Rm, @Rn //Store Byte Rm to @Rn
- CC0e-2nm1 MOV.W Rm, @Rn //Store Word Rm to @Rn
- CC0e-2nm2 MOV.L/Q Rm, @Rn //Store DWord Rm to @Rn
- CC0e-2nm3 -
- CC0e-2nm4 MOV.B Rm, @-Rn //Store Rm to Byte @Rn then Rn=Rn-1
- CC0e-2nm5 MOV.W Rm, @-Rn //Store Rm to Word @Rn then Rn=Rn-2
- CC0e-2nm6 MOV.L/Q Rm, @-Rn //Store Rm to DWord @Rn then Rn=Rn-4
- CC0e-2nm7 -
- CC0e-2nm8 TST Rm, Rn //Test Rm&Rn, updating SR.T
- CC0e-2nm9 AND Rm, Rn //And Rm and Rn, Storing result in Rn
- CC0e-2nmA XOR Rm, Rn //Xor Rm and Rn, Storing result in Rn
- CC0e-2nmB OR Rm, Rn //Or Rm and Rn, Storing result in Rn
- CC0e-2nmC -
- CC0e-2nmD -
- CC0e-2nmE -
- CC0e-2nmF -
- 3---
- CC0e-3nm0 CMPEQ Rm, Rn //Compare for Equality
- CC0e-3nm1 -
- CC0e-3nm2 CMPHS Rm, Rn //Compare for unsigned Greater/Equal
- CC0e-3nm3 CMPGE Rm, Rn //Compare for signed Greater/Equal
- CC0e-3nm4 -
- CC0e-3nm5 -
- CC0e-3nm6 CMPHI Rm, Rn //Compare for unsigned Greater
- CC0e-3nm7 CMPGT Rm, Rn //Compare for signed Greater
- CC0e-3nm8 SUB Rm, Rn //Subtract
- CC0e-3nm9 -
- CC0e-3nmA SUBC Rm, Rn //Subtract, Carry -> T
- CC0e-3nmB SUBV Rm, Rn //Subtract, Overflow -> T
- CC0e-3nmC ADD Rm, Rn //Add
- CC0e-3nmE ADDC Rm, Rn //Add with Carry, Carry -> T
- CC0e-3nmF ADDV Rm, Rn //Add, Overflow -> T
- 4---
- CC0e-4nm0 -
- CC0e-4nm1 -
- CC0e-4nm2 -
- CC0e-4nm3 -
- ...
- CC0e-4nmA (LDS Block)
- CC0e-4nmB -
- CC0e-4nmC SHAD.L/Q Rm, Rn
- CC0e-4nmD SHLD.L/Q Rm, Rn
- CC0e-4nmE (LDC Block)
- CC0e-4nmF -
- 5---
- CC0e-5nmd ? MOV.L/Q @(Rm,disp5), Rn //Load DWord From Rm+(4|8)*Disp
- Deprecate?: Redundant with CExx-6nm2/6nm3
- 6---
- CC0e-6nm0 MOV.B @Rm, Rn //B: Zero extend to QWord
- CC0e-6nm1 MOV.W @Rm, Rn //B: Zero extend to QWord
- CC0e-6nm2 MOV.L/Q @Rm, Rn //B: Extend to QWord
- CC0e-6nm3 MOV Rm, Rn
- CC0e-6nm4 MOV.B @Rm+, Rn
- CC0e-6nm5 MOV.W @Rm+, Rn
- CC0e-6nm6 MOV.L/Q @Rm+, Rn //B: Extend to QWord
- CC0e-6nm7 NOT Rm, Rn
- CC0e-6nm8 -
- CC0e-6nm9 -
- CC0e-6nmA NEGC Rm, Rn
- CC0e-6nmB NEG Rm, Rn
- CC0e-6nmC EXTU.B Rm, Rn
- CC0e-6nmD EXTU.W Rm, Rn
- CC0e-6nmE EXTS.B Rm, Rn
- CC0e-6nmF EXTS.W Rm, Rn
- (Q=0,B=0): EXTU.W / EXTS.W, Extend Word to DWord
- (Q=1,B=0): EXTU.WQ / EXTS.WQ, Extend Word to QWord
- (Q=1,B=1): EXTU.L / EXTS.L, Extend DWord to QWord
- 7---
- CC0e-7nii ? ADD #imm8, Rn //Add 8-bit Immed, supports Quad
- Deprecate?: Redundant with CEfi-7nii
- 8---
- 9---
- A---
- CC0e-Anmo ? MOV.L/Q Rm, @(Rn,Ro) //Store Rm to Rn+(4|8)*Ro
- Deprecate: Redundant with CExx-0nm6/0nm7
- B---
- CC0e-Bnmd ? MOV.L/Q @(Rm,Ro), Rn //Load From Rm+(4|8)*Ro
- Deprecate: Redundant with CExx-0nmE/0nmF
- C---
- D---
- CC0e-Enii ? MOV #imm8, Rn //Load 8-bit constant, supports Quad
- Deprecate?: Redundant with CEfi-Enii
- F---
Reorganization Note:
- A basic set of 3-addr ops has been re-added to the 8Exx block.
- This block is now specific to the 64-bit ISA.
- CC3e-bnst // 3-Address Binary Operator
- e: QNST
- Q: 0=Single/DWORD, 1=Double/QWORD
- N: Bit 4 for Rn
- S: Bit 4 for Rs (or Shift Bit 5)
- T: Bit 4 for Rt (or Shift Bit 4)
- CC3e-0nst ADD Rs, Rt, Rn // Rn=Rs+Rt
- CC3e-1nst SUB Rs, Rt, Rn // Rn=Rs-Rt
- CC3e-2nst MUL Rs, Rt, Rn // Rn=Rs*Rt
- CC3e-3nst AND Rs, Rt, Rn // Rn=Rs&Rt
- CC3e-4nst OR Rs, Rt, Rn // Rn=Rs|Rt
- CC3e-5nst XOR Rs, Rt, Rn // Rn=Rs^Rt
- CC3e-6nst SHLD Rs, Rt, Rn // Rn=Rs SHLD Rt
- CC3e-7nst SHLR Rs, Rt, Rn // Rn=Rs SHLR Rt (Unsigned)
- CC3e-8nst SHAD Rs, Rt, Rn // Rn=Rs SHAD Rt (Signed)
- CC3e-9nst SHAR Rs, Rt, Rn // Rn=Rs SHAR Rt (Signed)
- CC3e-Anst -
- CC3e-Bnst -
- CC3e-Cnst FADD FRs, FRt, FRn // FRn=FRs+FRt
- CC3e-Dnst FSUB FRs, FRt, FRn // FRn=FRs-FRt
- CC3e-Enst FMUL FRs, FRt, FRn // FRn=FRs*FRt
- CC3e-Fnst FDIV FRs, FRt, FRn // FRn=FRs/FRt
- e: QNST
Will follow a similar pattern to 8Exx-xxxx and CC0e-xxxx.
- CEei-xxxx
- e: qnmo / qnst
- Exact contents of 'e' depend on opcode.
- MOV.B/MOV.W/MOV.L: 'q' interpreted as a zero-extension flag.
- f: nmii, nqii
- Exact contents of 'f' depend on opcode.
- 0---
- CExx-0xx0 -
- CExx-0xx1 -
- CExx-0xx2 -
- CExx-0xx3 -
- CEeo-0nm4 MOV.B Rm, @(Rn,Ro)
- CEeo-0nm5 MOV.W Rm, @(Rn,Ro)
- CEeo-0nm6 MOV.L Rm, @(Rn,Ro)
- CEeo-0nm7 MOV.Q Rm, @(Rn,Ro)
- CExx-0xx8 -
- CExx-0xx9 -
- CExx-0xxA -
- CExx-0xxB -
- CEeo-0nmC MOV.B @(Rm,Ro), Rn
- CEeo-0nmD MOV.W @(Rm,Ro), Rn
- CEeo-0nmE MOV.L @(Rm,Ro), Rn
- CEeo-0nmF MOV.Q @(Rm,Ro), Rn
- CEed-1nmo MOV.L/Q Rm, @(Rn,Ro,disp4)
- 2---
- CEfd-2nm0 MOV.B Rm, @(Rn,disp6)
- CEfd-2nm1 MOV.W Rm, @(Rn,disp6)
- CEfd-2nm2 MOV.L Rm, @(Rn,disp6)
- CEfd-2nm3 MOV.Q Rm, @(Rn,disp6)
- CEfd-2nm4 FMOV.S FRm, @(Rn,disp6)
- CExx-2xx5 -
- CEfd-2nm6 FMOV.S @(Rm,disp6), FRn
- CExx-2xx7 -
- CExx-2xx8 -
- CEfj-2nm9 AND Rm, #imm6, Rn //Rn=Rm&Imm6
- CEfj-2nmA XOR Rm, #imm6, Rn //
- CEfj-2nmB OR Rm, #imm6, Rn //
- CExx-2xxC -
- CExx-2xxD -
- CEfj-2nmE MULL Rm, #imm6, Rn //Rn=Rm*Imm6 (Imm6 Zero-Ext)
- CEfj-2nmF MULL Rm, #-imm6, Rn //Rn=Rm*Imm6 (Imm6 One-Ext)
- 3---
- CEfi-3ni0 CMP/EQ #imm10, Rn
- CExx-3xx1 -
- CEfi-3ni2 CMP/HS #imm10, Rn
- CEfi-3ni3 CMP/GE #imm10, Rn
- CExx-3xx4 -
- CExx-3xx5 -
- CEfi-3ni6 CMP/HI #imm10, Rn
- CEfi-3ni7 CMP/GT #imm10, Rn
- CEfj-3nm8 SUB Rm, #imm6, Rn
- CEfj-3nm9 AND Rm, #-imm6, Rn
- CEfi-3nmA SHAL.Q Rm, #imm6, Rn
- CEfi-3nmB SHLL.Q Rm, #imm6, Rn
- CEfj-3nmC ADD Rm, #imm6, Rn
- CExx-3xxD -
- CEfi-3nmE SHAR.Q Rm, #imm6, Rn
- CEfi-3nmF SHLR.Q Rm, #imm6, Rn
- 4---
- CExx-4xx0 -
- CExx-4xx1 -
- CExx-4xx2 -
- CExx-4xx3 -
- CExx-4xx4 -
- CExx-4xx5 -
- CExx-4xx6 -
- CExx-4xx7 -
- CExx-4xx8 -
- CExx-4xx9 -
- CExx-4xxA -
- CExx-4xxB -
- CEfi-4nmC SHAD.L Rm, #imm6, Rn
- CEfi-4nmD SHLD.L Rm, #imm6, Rn
- CExx-4xxE -
- CExx-4xxF -
- CEed-5nmo MOV.L/Q @(Rm,Ro,disp4), Rn
- 6---
- CEfd-6nm0 MOV.B @(Rm,disp6), Rn
- CEfd-6nm1 MOV.W @(Rm,disp6), Rn
- CEfd-6nm2 MOV.L @(Rm,disp6), Rn
- CEfd-6nm3 MOV.Q @(Rm,disp6), Rn
- CEeo-6nm4 LEA.B @(Rm,Ro), Rn
- CEeo-6nm5 LEA.W @(Rm,Ro), Rn
- CEeo-6nm6 LEA.L @(Rm,Ro), Rn
- CEeo-6nm7 LEA.Q @(Rm,Ro), Rn
- CEfd-6nm8 LEA.B @(Rm,disp6), Rn
- CEfd-6nm9 LEA.W @(Rm,disp6), Rn
- CEfd-6nmA LEA.L @(Rm,disp6), Rn
- CEfd-6nmB LEA.Q @(Rm,disp6), Rn
- CEfd-6nmC MOVU.B @(Rm,disp6), Rn
- CEfd-6nmD MOVU.W @(Rm,disp6), Rn
- CEfd-6nmE MOVU.L @(Rm,disp6), Rn
- CEed-6nmF -
- CEfi-7nii / ADD #imm14, Rn
- CEii-7nii ADD #imm16, Rn //Rn=R16..R31
- CExx-8xxx
- CEii-9nii LDSH16 #imm16, Rn //Rn=(Rn<<16)+Imm16, Rn=R16..R31
- CExx-Axxx
- CExx-Bxxx
- CExx-Cxxx
- CExx-Dxxx
- CEfi-Enii / MOV #imm14, Rn
- CEii-Enii MOV #imm16, Rn //Rn=R16..R31
- CExx-Fxxx
The use of 64 and 48 bit blocks is possible, but look unlikely at this point.
XPFZ0, 64-bit Block
- CD7n-iiii-iiii-iiii ADD.Q #imm48, Rn //Add 48-bit Quad Constant
- CDA0-dddd-dddd-dddd BRA #imm48, Rn //Branch Disp48
- CDB0-dddd-dddd-dddd BSR #imm48, Rn //Call Disp48
- CDEn-iiii-iiii-iiii MOV.Q #imm48, Rn //Load 48-bit Quad Constant
- CF7n-iiii-iiii ADD.Q #imm32, Rn //Add 48-bit Quad Constant
- CFA0-dddd-dddd BRA #imm32, Rn //Branch Disp48
- CFB0-dddd-dddd BSR #imm32, Rn //Call Disp48
- CFEn-iiii-iiii MOV.Q #imm32, Rn //Load 48-bit Quad Constant