(ES) 3.2.3 Descripción de hardware de componentes IP personalizados - coffeebrain/Codesign_HW_SW GitHub Wiki
Managing the custom IP Component functionality is done by describing it using a hardware description language (HDL) such as Verilog, VHDL oy SystemVerilog.
Auto created Verilog module.
// avalon_module.v
`timescale 1 ps / 1 ps
module avalon_module
(
input avs_s0_address, // avs_s0.address
input avs_s0_read, // .read
output signed [31:0] avs_s0_readdata, // .readdata
input avs_s0_write, // .write
input signed [31:0] avs_s0_writedata, // .writedata
output avs_s0_waitrequest, // .waitrequest
input clock_clk, // clock.clk
input reset_reset, // reset.reset
input [31:0] conduit // conduit.new_signal
);
// ASSIGNS
assign avs_s0_readdata = 32'd0;
assign waitrequest = (waitFlag && avs_s0_read);
endmodule
Write Verilog interface
always@(posedge clock_clk)
begin
if(reset_reset)
begin
conduit <= 32'd0;
end
else if(avs_s0_write)
begin
case (avs_s0_address)
1'b0 : conduit <= avs_s0_writedata;
default : conduit <= conduit;
endcase
end
end
Read Verilog interface
always @(posedge clock_clk, posedge reset_reset)
begin: AVALON_READ_INTERFACE
if(reset_reset == 1)
begin
waitFlag <= 1;
end
else
begin
waitFlag <= 1;
if(avs_s0_read)
begin
case(avs_s0_address)
1'd0 : returnvalue <= conduit;
default : returnvalue <= 32'd0;
endcase
if(waitFlag == 1)
begin
waitFlag <= 0;
end
end
end
end