(ES) 1.5 Interfaces estándar - coffeebrain/Codesign_HW_SW GitHub Wiki
Las interfaces estándar son usadas para interconectar los componentes IP en Platform Designer.
Platform Designer soporta las siguientes interfaces estándar:
\begin{itemize} \item Avalon Memory-Mapped (Avalon-MM) \item Avalon Streaming Interface (Avalon-ST) \item Arm Advanced Microcontroller Bus Architecture Advanced eXtensible Interface (Arm AMBA AXI) \end{itemize}
** Aunque Platform designer permite estas 3 diferentes interfaces estándar, solo se explicará la interfaz de Avalon-MM en esta guía.
Required signals
Clock
Is a single signal that is used to synchronize one or more interfaces in a component. It is one of the most important signal as every interface needs it. This signal can be an input, if it comes from a clock generator, or an ouput if the component generates a signal clock (for example a prescaler or a PLL).
Reset
Is a single signal used to restart the component's function. It is also essential to have it in every component. This signal can be active low or active high, indicating that the reset works with a logical 0 or a logical 1, and It can be an input or an output.
Optional signals
Interrupt Signals
This signal is used to handle important events. There are sender (output) and receiver (input) interrupt interfaces. The first one is a single signal and comes from an slave to indicated the need of an interruption in order to handle a service, while the receiver interface is a 1-32 bits signal, where each bit is a single separate interrupt signal. The interrupts have a priority that is specified in Platform Designer when connecting the components, been 0 the highest priority.
Reset_req
Is a single signal that may come with the reset signal and works like a pre reset indicator useful to protect against asynchronous inputs. It can also be used as an input or an output.
Bus
Bridge
Advanced eXtensible Interface (AXI) Bridge
The DE0-Nano SoC HPS has the following bridges:
- HPS-FPGA Bridge.
- Lightweight HPS-FPGA Bridge.
- FPGA-HPS Bridge.
