Platform Designer comes with an IP catalog which is also able of generating new IP components through a tool named the Component Editor. If you don't know what an IP component is you can refer to 1.6 Componentes de Propiedad Intelectual (IP en inglés).

1. Open Quartus

2. Open Quartus Project

3. Open Platform Designer from Tools > Platform Designer.

4. When the file chooser windows prompt open your project's .qsys file.

5. On the IP Catalog tab click on the New... button.

6. In the new window fill the Name:, Display name: and any other field you consider for your component's creation.

7. Click Finish... to save your design.

8. Then in the new Save Changes windows click on Yes, Save. A new tcl file should be created with the components name that you've chosen.

9. Search for the new IP component in the Project or Library Section at the IP Catalog tab. If you filled the Group field when creating a section with this name must have the newly created component.

IMG

10. Chose your IP component and click on Edit....

IMG

From this step on there are several ways of configuring your IP components:

• Manual Creation of signals
• Using a template
• With a Verilog, VHDL or System Verilog existing file

11. From the Templates menu choose Add Typical AXI4 Slave.

12. Go to the Signals & Interfaces tab.

13. See the newly created interfaces and signals, add more if you need.

14. You can create a Conduit if you need to expose an input or output to the FPGA portion.

15. A new interface is added.

16. Change the name of the new interface as desired.

17. Associated a reset signal to the interface.

18. Create a new conduit signal.

19. Change the name of the new conduit signal as desired.

20. Change the signal width as desired.

21. The signals must be now ready (add others if you need it).

22. Create synthesis file from the signals and interfaces in the File window.

23. A new emergent window appear to create the HDL template.

24. Choose your destination path.

25. You can open the file explorer to choose your file desination.

26. Save you HDL file.

27. Finish the IP component design by clicking on Finish....

28. Save the changes by clicking on Yes, Save option.

29. A new window showing the saving process appears.

30. After returning to Platform Designer main window click on Add... from the IP Catalog tab.

31. A new window for adding component appears (configure if parameters where added to IP design).

32. A new disconnect component appears in the System Contents tab.

33. Make the desired conections.

34. Export your Conduit signals by double clicking in the Export column from the Conduit row.

35. The Conduit is succesfully exported.

36. If two components share the same address an error will appear. If no you can jum to step 39.

37. Assign new address manually, or automatically by going to System > Assign Base Addresses.

38. Save the system.

39. Then click on Generate HDL... button.

40. Click on Generate HDL....

41. A progress bar with messages will appear while generating.

36. When the generation ends a message similar to the following will appear.

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• Making Qsys Component

Return to 3.2 Hardware Configuration and Synthetization