IP Generation - ORKA-HPC/orka-hpc-llp GitHub Wiki

Content of this page: Instructions on how to use the ORKA-HPC LLP IP Builder

ORKA-HPC LLP IP Builder

ORKA-HPC LLP includes an IP Builder tool to generate IP (in IP-XACT format) from C/C++ source code. It takes the source files and (depending on the targeted FPGA) passes them to either Vivado HLS or Intel HLS.

C/C++ source code requirements

The IP Builder does not modify the C/C++ source code. In order for the IPs to be usable with the remaining ORKA-HPC toolchain, the source code must be annotated with pragmas and makros already. For further code requirements and limitations please refer to Vivado HLS and Quartus HLS documentation respectively.

Xilinx

The ORKA-HPC LLP on-FPGA-infrastructure uses the AMBA AXI4-Lite interface for control and AMBA AXI4 interface for data transfers. The top-level function must be annotated with the corresponding pragmas.

  • IP control via AXI4-Lite is enabled by adding the following line to the top level function: #pragma HLS INTERFACE s_axilite port=return
  • You may map parameters to the FPGA's DDR memory by adding #pragma HLS INTERFACE m_axi depth=64 offset=slave port=[parameter name]

Intel

On Intel FPGAs the ORKA-HPC LLP on-FPGA-infrastructure uses Avalon interfaces. In order to allow for control and data transfers via the ORKA-HPC GenericDriver, the top level function and parameters must be annotated with makros defined in HLS/hls.h provided by the Intel HLS compiler.

  • Prefix the top level function definition with hls_avalon_slave_component component. This will tell the HLS compiler that this is a top-level function and that the Avalon interface shall be used for control.
  • Prefix all parameters with hls_avalon_slave_register_argument
  • All parameters that shall be mapped to the FPGA's DDR memory must be of type ihc::mm_master

For example top-level functions please have a look at our examples:

  • [orka-hpc-root-dir]/example/ip_example_intel for Intel
  • [orka-hpc-root-dir]/example/exampleip for Xilinx

How to use build_ip.sh

Before you run the tool please make sure that the HLS compiler is in your PATH and that a valid license is set. We tested Xilinx Vivado (Vitis) versions 2018.2 through 2020.2. For Intel FPGAs we reccomend using Quartus version 21.1.

  • For Xilinx FPGAs:
    • source [Vivado install dir]/Vivado/2019.1/settings64.sh
    • export LM_LICENSE_FILE=[path to license file] # for local license file
    • export LM_LICENSE_FILE=[port]@[license server address] # for remote license server
  • For Intel FPGAs:
    • export INTEL_FPGA_DIR=[Quartus install dir]
    • source [orka-llp-root-dir]/hw/build_ip/prepare_intel_tools.sh

Invocation

[orka-llp-root-dir]/hw/build_ip/build_ip.sh [target_board] \
    [export_dir] \
    [src_dir] \
    [tlf] \
    [clock] \
    [cflags] \
    [sourcefiles]

Meaning of arguments

  • target_board: One of the supported boards listed in [orka-llp-root-dir]/hw/build_ip/board_support.
  • export_dir: The export dir generated files will be written to.
  • src_dir: Path to C/C++ source files.
  • tlf: Top-level function = entry point for HLS.
  • clock: target clock frequency for this kernel (only applies to Xilinx FPGAs).
  • cflags: Additional flags to be passed to the HLS compiler. (Pass "" for no args)
  • sourcefiles: List of C/C++ source files to be processed (inside src_dir).

Once your IPs are built you may continue with setting up your hardware configuration using the ORKA-HPC LLP HW Configurator.