Bitstream Generation - ORKA-HPC/orka-hpc-llp GitHub Wiki
Content of this page: Instructions on how to use the ORKA-HPC LLP Bitstream Generator
ORKA-HPC LLP Bitstream Generator
The Bitstream Generator consists of a set of bash and tcl scripts and generates - as the name suggests - bitstreams with a single command. Depending on the target platform it runs and instructs either Xilinx Vivado or Intel Quartus in order to build the hardware design.
We currently support the following FPGA boards:
- Xilinx:
- Intel:
Partial reconfiguration is supported and enabled in the Intel Arria 10 design. The tool rebuilds the static design if necessary and generates bitstreams for the partial reconfiguration Zone for each kernel. These may later be executed sequentially without the need to reconfigure the entire FPGA. This also accelerates the bitstream generation process.
For Xilinx FPGAs we do not support partial reconfiguration (yet). The infrastructure is however very flexible and may be customized through the ORKA-HPC HW Configurator. This allows for different configurations ranging from lightweight designs (for example for very small FPGAs) up to designs with high connectivity (PCIe, Ethernet, USB) and including soft core processors and caches.
How to run:
Before you run the tool please make sure that Xilinx Vivado or Intel Quartus (depending on your target platform) is in your PATH and that a valid license is set. We tested Xilinx Vivado (Vitis) versions 2018.2 through 2020.2. For Intel FPGAs we reccomend using Quartus version 21.1.
The Bitstream Generator reads the HW configuration from JSON files. You may reuse previously generated files or configure a new design with the ORKA-HPC HW Configurator. Then simply run the bash script and pass the path to the configuration files as the first argument:
[orka llp root dir]/hw/generate_bitstream.sh [path to config files]