Yocto - MarekBykowski/readme GitHub Wiki

SW stack and something to run it on

Cortex-A Profile CPU

The idea behind these undertakings is very simple: facilitate BSP ARM{v8,v7} development without the ARM HW underneath from reset/ROM bootloader all the way up to Linux OS.

To serve the purpose you need a simulator and SW stack/ARM BSP to be put on the simulator:

FastModel/SystemC simulator/s https://developer.arm.com/documentation/100966/1127/Introduction-to-FVPs/Types-of-FVP?lang=en, license-managed FVPs, or free-of-charge FVPs.
For arm64 (aarch64) - BSP components/SW stack is: BL1 (ROM bootloader), BL2 (SPL U-Boot), BL31 (EL3 Runtime Services/Secure Monitor), BL33 (U-Boot), Linux Kernel, device-tree, and rootfs. And optionally BL32 (Secure-EL1 Payload) in secure state. BL32 runs at S-EL1
For arm32 (aarch34) - BL1 (Trusted ROM), BL2 (Trusted Boot Firmware), BL32 (EL3 Runtime Services), BL33 (Non-trusted Firmware/U-boot)
For building the SW stack for ARM AEM we use Yocto meta layer meta-arm https://git.yoctoproject.org/meta-arm and poky distro https://git.yoctoproject.org/poky

Cortex-M profile CPU

ROM boot (in chip)
↓
(optional) user bootloader
↓
startup.s
↓
SystemInit()
↓
RTOS (optional)
↓
Application

Cortex-M7 sample boot up flow

https://developer.arm.com/community/arm-community-blogs/b/architectures-and-processors-blog/posts/cortex-m-resources

Cheetsheet for arm{v7,v8}-a

Cheatsheet for armv7-a

Free-of-charge FVPs are:

FVP-AEM (Fixed-Virtual-Platform Architecture-Envelope-Models)
- AEMs are generic FVPs suitable for early Arm Architecture exploration
- refer to often as fvp base see details fvp‐base

Excerpt from ARM

Fast Models FVPs are based on the following platforms:

Base Platform.
BaseR Platform.
Arm® Versatile™ Express development boards.
Arm® MPS2 or Arm® MPS2+ platforms, for Cortex®‑M series processors.

Corstone Ecosystem FVP, the IoT systems https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/IoT%20FVPs
- Corstone-1000:
  - provides a flexible compute architecture that combines Cortex-A and Cortex-M processors with the optional CryptoCell-312 cryptographic accelerator
  - pre-verified Corstone SSE-710 subsystem that provides a flexible compute architecture that combines Cortex®‑A and Cortex®‑M processors
  - support for Cortex®‑A32, Cortex®‑A35 and Cortex®‑A53 processors
  - two expansion systems for M-Class (or other) processors for adding sensors, connectivity, video, audio and machine learning at the edge
  - supported from Yocto
  - details
- Corstone-500; discontinued support from Yocto
- Corstone-300
  - Aligned with the Arm MPS3 development platform
  - The model is based on the Cortex-M55 processor and offers a choice of the Ethos-U55 and Ethos-U65 processors
  - Supported from TF-M and Arm Keil CMSIS packs ARM.V2M_MPS3_SSE_300_BSP
- Corstone-310
  - reference subsystem for a secure SSE-310 SoC aligned with the Arm MPS3 development platform
  - model is based on a Cortex-M85 processor, an Ethos-U55 neural network processor, and the DMA-350 Direct Memory Access controller
  - Supported from TF-M and Arm Keil CMSIS packs
- Corstone-315
  - reference subsystem for a secure SSE-315 SoC aligned with the Arm MPS4 development platform
  - model is based on a Cortex-M85 processor, Arm DMA-350, Arm Mali-C55 ISP, and the second-generation NPU, Arm Ethos-U65
  - TF-M and CMSIS pack "SSE_315_BSP"
- Corstone-320
  - reference subsystem for a secure SSE-320 SoC aligned with the Arm MPS4 development platform
  - model is based on a Cortex-M85 processor, Arm DMA-350, Arm Mali-C55 ISP and the third-generation NPU, Arm Ethos-U85.
  - TF-M and CMSIS pack "SSE_320_BSP"

ARM Corstone-1000

HW overview

Pre-verified Corstone SSE-710 subsystem that provides a flexible compute architecture that combines Cortex®‑A and Cortex®‑M processors.
Support for Cortex®‑A32, Cortex®‑A35 and Cortex®‑A53 processors.
Two expansion systems for M-Class (or other) processors for adding sensors, connectivity, video, audio and machine learning at the edge
System and security IPs to build a secure SoC for a range of rich IoT applications, for example gateways, smart cameras and embedded systems.
Integrated Secure Enclave providing hardware Root of Trust and supporting seamless integration of the optional CryptoCell™-312 cryptographic accelerator
Designed to target PSA Certified Level 2 and System Ready IR certifications.

Docs old https://corstone1000.docs.arm.com/en/corstone1000-2023.06/index.html
Docs latest https://corstone1000.docs.arm.com/en/corstone1000-2024.11/index.html
https://corstone1000.docs.arm.com/en/latest/
HW overview https://developer.arm.com/documentation/102360/0000/Overview-of-Corstone-1000/Corstone-1000
Corstone-1000 SW stack

ARM Corstone-300

CMSIS-Toolbox

CMSIS-Toolbox (Common Microcontroller Software Interface Standard) that provides command-line tools for project creation and build of embedded applications that utilize software packs.

https://open-cmsis-pack.github.io/cmsis-toolbox/#

https://github.com/Open-CMSIS-Pack/csolution-examples/tree/main

ARM Keil uVision

Go to https://www.keil.arm.com/devices/ and select the pack. The packs include sample examples.

https://www.keil.arm.com/mdk-community/
YouTube from installing https://www.youtube.com/watch?v=WirMEYIVATo

Go to where the cbuild is and interrogate its env.

EU+xxbykowm@WPF2VVQYL /cygdrive/c/Users/xxbykowm/AppData/Local/Keil_v5/ARM/cmsis-toolbox/bin
$ ./cbuild list environment
CMSIS_PACK_ROOT=C:/Users/xxbykowm/AppData/Local/Arm/Packs
CMSIS_COMPILER_ROOT=C:/Users/xxbykowm/AppData/Local/Keil_v5/ARM/cmsis-toolbox/etc
Long pathname support=enabled
cmake=C:\Program Files\CMake\bin\cmake.exe, version 3.31.5
ninja=C:\Users\xxbykowm\AppData\Local\Microsoft\WinGet\Links\ninja.exe, version 1.12.1

The Issue I had was --toolchain (eg. cbuild Hello.csolution.yml --packs --context-set --toolchain AC6 --rebuild ) from cmdline neither compiler in *.csolution.yml file wasn't set. The Keil uVision then looked for the compiler missing and error'ed.

Arm Keil Studio Pack (MDK v6) for Visual Studio Code

https://github.com/Arm-Software/vscode-keil-studio-pack/blob/main/README.md

Cortex-M33 and SSE-200 IP

Sample BootUp flow for Cortex-A53

Sample BootUp flow for Cortex-M

+--------------------------------------------------+
|                  Application                     |
|         (Bare metal or RTOS tasks)              |
+--------------------------------------------------+
|                    RTOS                          |
|          (FreeRTOS, ThreadX, etc.)               |
+--------------------------------------------------+
|              main() / C Runtime                  |
+--------------------------------------------------+
|              SystemInit()                        |
|       (Clock, FPU, memory setup)                 |
+--------------------------------------------------+
|              Reset_Handler                       |
|  - Copy .data                                    |
|  - Zero .bss                                     |
|  - Call SystemInit                               |
+--------------------------------------------------+
|              Vector Table                        |
|  SP value | Reset_Handler | ISRs ...             |
+--------------------------------------------------+
|              Boot ROM (in chip)                  |
|  - Loads initial SP                              |
|  - Jumps to Reset_Handler                        |
+--------------------------------------------------+
|                    Hardware                      |
+--------------------------------------------------+

Cache coherency

                 ┌───────────────────────────────┐
                 │        DRAM (Main Memory)     │
                 └───────────────┬───────────────┘
                                 │
                         ┌───────▼────────┐
                         │   L3 Cache     │   (optional)
                         │  (Shared)      │
                         └───────┬────────┘
                                 │
                         ┌───────▼────────┐
                         │   L2 Cache     │   (Shared)
                         │  + Snoop Logic │
                         └───────┬────────┘
                                 │
                ┌────────────────┴────────────────┐
                │     Coherent Interconnect       │
                │   (CCI / CMN / SCU / ACE)       │
                └───────────────┬─────────────────┘
                                │
         ┌──────────────────────┼──────────────────────┐
         │                      │                      │
 ┌───────▼───────┐      ┌───────▼───────┐      ┌───────▼───────┐
 │    Core 0     │      │    Core 1     │      │    Core N     │
 │               │      │               │      │               │
 │  L1 I-Cache   │      │  L1 I-Cache   │      │  L1 I-Cache   │
 │  L1 D-Cache   │      │  L1 D-Cache   │      │  L1 D-Cache   │
 │ (MESI states) │      │ (MESI states) │      │ (MESI states) │
 └───────────────┘      └───────────────┘      └───────────────┘

Core0 (L1 cache controller)  ← responds to snoop
Core1 (L1 cache controller)  ← responds to snoop
Core2 (L1 cache controller)  ← responds to snoop
         ↑
   Coherent Interconnect
   (SCU / CCI / CMN)
         ↑
       DRAM

SoC architecture/Block Diagram and Memory Map

Interrconnects AHB (AMBA 2/3) AXI (AMBA 3/4/5)

AHB, shared interconnect (addres and data)

Master1 ─┐
Master2 ─┼─── BUS ─── Slave1
DMA     ─┘           Slave2

AXI - 5 channels

            ──────────────┐
CPU ──────▶│              │────▶ SRAM
DMA ──────▶│ AXI          │────▶ SDRAM
GPU ─────▶ │ Interconnect │────▶ Periph
           |              │
           └──────────────┘

Items:

kernel config
bitbake -c devshell

References:

[1] ARM Fast Models
[2] https://docs.yoctoproject.org
[3] Working with your own kernel sources https://docs.yoctoproject.org/kernel-dev/common.html#working-with-your-own-sources
[4] What is Poky? Poky
[5] Simple howto https://a4z.gitlab.io/docs/BitBake/guide.html
[6] Yocto qemu https://docs.yoctoproject.org/dev-manual/qemu.html
[7] Common tasks, eg. customizing image, adding/updating recipe https://docs.yoctoproject.org/dev-manual/common-tasks.html