The platform mapping file describes the mapping of latency-insensitive modules onto a Environment. An example is

model -> FPGA0;
common_services -> FPGA0;
connected_application -> FPGA0;
hardware_system -> FPGA0;
test_a -> FPGA0;
test_c -> FPGA0;
test_b -> FPGA1;
test_d -> FPGA1;

Modules are mapped to two hypothetical FPGAs, FPGA0 and FPGA1. Other FPGAs may exist in the environment, but no portion of the user program will be mapped. These FPGAs may be used for communications route through and their resources may be incorporated into the design.

Module names are currently constrained to correspond to awb modules declared as a SYNTH_BOUNDARY in its .awb file. In practice, this means that latency insensitive modules must be unique.

Future refinements to the compiler should eliminate the need for this mapping file.