Environment files describe the network of FPGAs to which a MultiFPGA program can be mapped. The following gives an example of how an environment is described:

master FPGA0 "config/pm/multifpga/fpga_submodels/fpga0_4.apm";
   FPGA2 -> vplat.llpint.physicalDrivers.simCommDrivers[2];
   FPGA2 <- vplat.llpint.physicalDrivers.simCommDrivers[2];
endmaster

platform FPGA1 "config/pm/multifpga/fpga_submodels/fpga1_4.apm";
   FPGA2 -> vplat.llpint.physicalDrivers.simCommDrivers[2];
   FPGA2 <- vplat.llpint.physicalDrivers.simCommDrivers[2];
endplatform

platform FPGA2 "config/pm/multifpga/fpga_submodels/fpga2_4.apm";
   FPGA0 -> vplat.llpint.physicalDrivers.simCommDrivers[0];
   FPGA0 <- vplat.llpint.physicalDrivers.simCommDrivers[0];
   FPGA1 -> vplat.llpint.physicalDrivers.simCommDrivers[1];
   FPGA1 <- vplat.llpint.physicalDrivers.simCommDrivers[1];
endplatform

In this environment there are three FPGAs platforms connected in a linear arrangement (FPGA0 <→ FPGA2 <→ FPGA1) in which the central FPGA has a communication link with the other FPGAs.

Each platform contains a description of its service set, the APM file listed in quotations, and a set of connections to other FPGAs in the environment. The connection set is denoted using the arrow (<- and ->) notation using the form:

platform [<-|→] driver;

Here the driver refers to the specific path in the platform service set where the physical interconnect driver will be found, and vector formats are supported. The LIM compiler uses these paths directly when it synthesizes inter-FPGA routers. The drivers must have a specific FIFO-like interface:

In principal, any physical transport medium may be used to communicate between FPGAs in the environment, so long as this medium support guaranteed, in-order delivery of messages. Media include LVDS or single-ended wires, SERDES, and ethernet. The physical media may have arbitrary physical width, and may be ganged together to form high-bandwidth physical communication channels.

Although the arrow notation permits the description of directed graphs of FPGAs, the current LIM compiler requires that FPGAs must be connected by a bi-direction communication medium.

Platforms are wrapped by the master/endmaster or platform/endplatform keywords. The master platform has a connection to the software side of the hybrid LEAP program. Currently, multiple master platforms are not supported.