DataStorm DAQ Golden Hardware Reference Design (GHRD) - ArrowElectronics/arrow-soc-workshops GitHub Wiki

The Golden Hardware Reference Design (GHRD) for the DataStorm DAQ provides a starter reference design. It includes a Platform Designer reference design that maps a number of HDL based FPGA peripherals to the HPS (Hard Processor System) and the ARM Cortex-A9 processors. This design is intended as a starting point for new designs.

1. Overview
2. HPS Address Maps
3. Quartus build
4. Creating project framework
5. Creating Processor System
6. Adding other Peripherals
7. Creating top-level design

The Golden Hardware Reference Design is an important part of the GSRD and consists of the following components:

• ARM Cortex®-A9 MPCore HPS
• Onchip RAM
• One user push-button inputs
• Two user I/O for LED outputs
• JTAG Master
• JTAG UART
• System ID

Resources

• Quartus Info
• Quartus Intro video
• Platform Designer
• Scripting
• Design Constraints
• Design Compilation
• Design Optimization
• Design Recommendations
• Programming Intel FPGAs
• Debug Tools
• Cyclone V HPS Technical Reference Manual
• Cyclone V Overview
• Cyclone V Datasheet
• Cyclone V Handbook
• Cyclone V Transceivers
• Intel FPGA Training Courses

This section presents the address maps as seen from the HPS processor (Cortex-A9) side.

The memory map of soft IP peripherals, as viewed by the HPS (Cortex-A9) processor, starts at HPS-to-FPGA address offset 0xC000_0000.
The offset of each peripheral in the FPGA portion of the SoC is as follows:

Periheral	Address Offset	Size (bytes)	Attribute
onchip_memory2_0	0x0_0000	64K	On-chip RAM as scratch pad

The memory map of system peripherals in the FPGA portion of the SoC as viewed by the HPS (Cortex-A9) processor, which starts at the lightweight HPS-to-FPGA base address 0xFF20_0000, is as follows:

Periheral	Address Offset	Size (bytes)	Attribute
sys_id	0x1_0000	8	Unique system ID
led_pio	0x1_0040	8	LED output display
dipsw_pio	0x1_0080	8	Push button input
button_pio	0x1_00c0	8	DIP switch input
jtag_uart	0x2_0000	8	JTAG UART console

The HPS exposes 64 interrupt inputs for the FPGA logic. The following table lists the interrupts from soft IP peripherals to the HPS interrupt input interface.

Periheral	Interrupt Number	Attribute
dipsw_pio	f2h_irq0 [0]	2 DIP switch inputs (falling edge)
button_pio	f2h_irq0 [1]	1 push button inputs (either level)
jtag_uart	f2h_irq0 [2]	JTAG UART

Use Quartus® Prime Lite version 20.1. for the build. A full build should take between 25 to 60 minutes. The Build instructions will be described in a later section,.

The build will produce the following items:

File	Description
.sof	SRAM Object File - FPGA programming file, resulted from compiling the FPGA hardware project
Handoff	Folder containing a description of the hardware to be used by the Preloader Generator

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