Goal

This week's goal was to design (or vibe-code) an SPI interface to hook in our Verilog with Python. The first thing I attempted to do was design an SPI interface that took the output of my network and sent it over SPI.

Verilog Design

I told Gemini to design an SPI interface in a separate module that would take the output of my network and send it over SPI to software in order to characterize performance. I also asked it to generate a testbench that I could test in EDA Playground. I've had more success with EDA Playground after switching to the more advanced simulators, specifically Synopsys VCS. This has allowed me to fully validate my design up until now.

Theoretically, I should just be sending 8 bytes as every output of my decoder. We have 2 frames and 4 mel spectrograms as I greatly reduced the network to provide a proof of concept. Is this challenging to send 8 bits over SPI after the decoder says it's done? Apparently it is for Gemini because both the module and testbench are around 300 lines of code. It seems absurd. I've decided to limit my time doing codefests to 3 hours. I don't learn anything just asking an LLM to debug its own code into oblivion, and I could spend this time actually trying to understand how things are working and help debug it on my own. Unfortunately, the task that I started out with (VAE decoder for audio) has proven to be too complicated for the LLM.

After an hour and a million bugs later, I switched from Gemini back to ChatGPT o4-mini-high. I believe I got things working. Overall, the module is an SPI slave interface that continuously transmits words. When cs_n goes low, the first data is loaded and it outputs bits (starting with the MSB) on the miso line. On every falling edge of sclk, it prepares the next bit to be transmitted until the end of a word, upon which it loads the next word from data_in and repeats.

In EDA Playground I tested 8 words and got the following:

Word 0: got=0xaaaa, exp=0xaaaa
Word 1: got=0x1234, exp=0x1234
Word 2: got=0xf0f, exp=0xf0f
Word 3: got=0xff, exp=0xff
Word 4: got=0x8001, exp=0x8001
Word 5: got=0x7fff, exp=0x7fff
Word 6: got=0x55aa, exp=0x55aa
Word 7: got=0xdead, exp=0xdead

So it looks like it's working. The next step is to integrate it with the rest of the module. But first I need to go through and make sure my state machine is working.

Ongoing Project

I've decided to greatly reduce my network. I'm going to do a toy version of my final network and go through the workflow for that as my final project. This has proven to be challenging enough. I have tested all my layers, and they all work correctly. The issue now is hooking them up with a state machine. I've nearly completed that with all but the last layer implemented. My final network is:

relu(fc(4 latent)) → upsample → relu(conv1) → relu(conv2) → relu(conv3) → spi → cpu

When that is complete, I'll hook up the SPI interface and start testing some speeds.