Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

Execution of nonblocking assignments can be viewed as a two-step process:

1. Evaluate the RHS of nonblocking statements at the beginning of the time step.
2. Update the LHS of nonblocking statements at the end of the time step.

• Guideline #1: When modeling sequential logic, use nonblocking assignments.
• Guideline #2: When modeling latches, use nonblocking assignments.
• Guideline #3: When modeling combinational logic with an always block, use blocking assignments.
• Guideline #4: When modeling both sequential and combinational logic within the same always block, use nonblocking assignments.
• Guideline #5: Do not mix blocking and nonblocking assignments in the same always block.
• Guideline #6: Do not make assignments to the same variable from more than one always block.
• Guideline #7: Use $strobe to display values that have been assigned using nonblocking assignments.
• Guideline #8: Do not make assignments using #0 delays.

Verilog "stratified event queue"

Verilog is permitted to simulate the always blocks in any order

A Linear Feedback Shift-Register (LFSR) is a piece of sequential logic with a feedback loop.

Making multiple assignments to the same variable from more than one always block is a Verilog race condition, even when using nonblocking assignments.

• Myth: “Using the $display command with nonblocking assignments does not work”
• Truth: Nonblocking assignments are updated after all $display commands

• Myth: “#0 forces an assignment to the end of a time step”
• Truth: #0 forces an assignment to the "inactive events queue"
• Guideline: Use $strobe to display values that have been assigned using nonblocking assignments.

• Myth: “Making multiple nonblocking assignments to the same variable in the same always block is undefined”
• Truth: Making multiple nonblocking assignments to the same variable in the same always block is defined by the Verilog Standard. The last nonblocking assignment to the same variable wins!