• 芯片中的数学——均衡器EQ和它在高速外部总线中的应用

udev

• https://en.wikipedia.org/wiki/Udev
• https://wiki.archlinux.org/index.php/Udev
• https://wiki.debian.org/udev
• Tutorial on how to write basic udev rules in Linux
• Beginners Guide to Udev in Linux

Serial Programming

• https://en.wikibooks.org/wiki/Serial_Programming

• https://en.wikibooks.org/wiki/Serial_Programming/Serial_Linux

• https://en.wikibooks.org/wiki/Serial_Programming/termios

• https://en.wikibooks.org/wiki/Robotics

• http://man7.org/linux/man-pages/man3/termios.3.html

PLC

• https://en.wikipedia.org/wiki/Programmable_logic_controller
• 可编程逻辑控制器
• https://github.com/kyle-github/libplctag
• What is the difference between a Canbus and a PLC?

HslCommunication

• https://github.com/dathlin/HslCommunication

modbus

• https://en.wikipedia.org/wiki/Modbus

com

minicom

• linux minicom usb串口
• Ubuntu安装配置串口通讯工具minicom&&cutecom
• Minicom 使用初步
• minicom安装、配置、及使用中遇到问题
• linux超级终端minicom的使用方法

secureCRT

• secureCRT用串口连接mini2440方法
• 让SecureCRT显示光标所在处（光标闪烁）
• SecureCRT让光标闪烁，确定其位置（转）

copy

• File transfer over a serial line
• Copy text in minicom doesn't get copied completely
• How can I transfer a binary file using minicom and a serial connection?

JTAG

• JTAG调试原理
• JTAG JLink ULINK ST-LINK仿真器区别
• https://elinux.org/JTAG
• Debugging the Linux kernel with JTAG

Flash

• NorFlash、NandFlash、eMMC比较区别

I2C

• https://en.wikipedia.org/wiki/I%C2%B2C
• https://baike.baidu.com/item/I2C%E6%80%BB%E7%BA%BF
• 诸如SPI、 I2C、USART等协议有什么共同点和区别啊？什么时候该用什么？

Memory-mapped IO

• What is the difference between DMA and memory-mapped IO?

IOMMU

• https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit

Linux

• Linux下用文件IO的方式操作GPIO（/sys/class/gpio）

udev

• Allow non-root user to read/write /dev files

NVMe

• https://en.wikipedia.org/wiki/NVM_Express

• NVMe (non-volatile memory express)

• https://github.com/enfiskutensykkel/ssd-gpu-dma

• Nvidia GPUs gain direct access to NVMe storage

• 一篇最详尽的NVMe/TCP技术疑问解答

InifiBand

• infiniband学习总结
• 一文掌握InfiniBand技术和架构

AXI

• Introduction to AXI Protocol: Understanding the AXI interface

• [AXI latency 理解【转】](https://www.cnblogs.com/sky-heaven/p/16280850.html)

• AMBA低功耗接口（一）Q_Channel

• AMBA低功耗接口（二）P_Channel

• AXI总线学习-------从零开始详细学-------------连载（1）

• AXI总线学习------从零开始详细学-----------连载（2）axi protocol 通道分类

• AXI总线学习-------从零开始详细学-------------连载（3）AXI通道信号大全，握手简介

• AXI总线学习-------从零开始详细学-------------连载（4）握手机制简介，内部握手

• AXI总线学习-------从零开始详细学-------------连载（5）各通道握手信号，握手机制相互关系

• AXI总线学习-------从零开始详细学-------------连载（6）读写处理架构，burst介绍，burst细节定义（burst size burst length）

• AXI总线学习-------从零开始详细学-------------连载（7）读写处理架构，burst介绍，burst细节定义（burst type burst address）

• AXI总线学习-------从零开始详细学-------------连载（9）读数据通中字节不变性

• AXI总线学习-------从零开始详细学-------------连载（10）读写响应

• AXI总线学习-------进阶过程STEP1----------连载（11）AXCACHE

• 【AXI】解读AXI协议中的burst突发传输机制

• 数字芯片设计——握手与反压

• Axi stream理解与总结

Outstanding

• Transfer behavior and transaction ordering

• AXI outstanding理解

• AXI 总线基本概念1 - 如何理解outstanding传输

ring bus

• How do Intel CPUs that use the ring bus topology decode and handle port I/O operations
• 破茧化蝶，从Ring Bus到Mesh网络，CPU片内总线的进化之路

DDR

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• What are the data transfer rates for DDR, DDR2, DDR3 and DDR4?

DDR SDRAM

DDR SDRAM is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM consists of a single 2n–bit wide data transfer at the internal DRAM array during one clock cycle, and two corresponding n–bit wide data transfers at the I/O pins, each during one-half of the clock cycle. Therefore, the internal data bus is twice as wide as the external interface would indicate.

Read and write accesses to the DDR SDRAM are burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length can be programmed to 2, 4, or 8 locations. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered with an Active command are used to select the bank and row to be accessed. The address bits registered with a Read or Write command are used to select the bank and the starting column location for the burst access. An Auto Precharge function may be enabled to provide a row precharge that is initiated at the end of the burst access.

Because of the high data-transition speeds, on a heavily loaded bus the low voltage TTL interface cannot be used for the I/O buffers. For that reason, DDR SDRAM uses an I/O interface called SSTL_2 (Stub-Series Terminated Logic).

Read Operation

Burst read operations are initiated with a Read command. The starting column and bank addresses are provided with this command. The Auto Precharge operation is either enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed will start precharge at the completion of the burst operation.

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• 深入内存/主存：解剖DRAM存储器