Intel Xe - yiliu30/yi GitHub Wiki
| Architecture | Target Use | Dev | Key Features |
|---|---|---|---|
| Xe-LP (Low Power) | Client | 11th GEN (Tiger Lake, TGL) | Integrated graphics for 11th-gen Intel Core, Iris Xe MAX mobile GPUs, Sampler Feedback, AV1 decoding |
| Xe-LPG (Low Power Graphics) | Client | MTL (iGPU) | Low power variant for integrated GPUs(iGPU) in Meteor Lake(MTL) and Arrow Lake processors, optimized for lower wattage and higher performance per watt |
| Xe-HPG (High Performance Graphics) | Client/Data Center? | Arc (DG2) Data Center GPU Flex 170 |
Enthusiast gaming, hardware-accelerated ray tracing, DirectX 12 Ultimate, XeSS, 16 vector and matrix engines per Xe-core |
| Xe-HP (High Performance) | Data Center | Datacenter applications, optimized for FP64 performance, multi-tile scalability | |
| Xe-HPC (High Performance Compute) | Data Center/HPC | Data Center GPU Max (Ponte Vecchio, PVC) | High-performance computing, 8 vector and 8 matrix engines per Xe-core, 512 KB L1 cache |
| Xe2 |
https://hc33.hotchips.org/assets/program/conference/day2/hc2021_pvc_final.pdf
- Dot Product Accumulate Systolic, DPAS https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html
By ChatGPT
Xe -> Xe2 ->