Release notes - wvoice/Accelerators GitHub Wiki

This is the sixth release in the series of releases for the NetFPGA-10G beta community. It has the following new features:

• Updated DMA core for reference projects
  • The reference projects (reference_nic,reference_nic_1G,reference_switch,reference_switch_lite and reference_flash) have been updated with a new DMA core. The reference_nic project in the previous release_4.7.1 (utilizing the OPED core) has been moved to the contrib_projects as nic_oped.
• SW update (nf10_switch) for Reference Switch and Reference Switch Lite
  • New software tools to read the LUT hit and miss registers can be found inside the the specific project's /sw/host/nf10_switch folder.
• Production test
  • Updated the config file and production scripts to support different com ports for UART testing.
• New naming convention to identify projects using OPED core in the contrib_projects
  • "{project_name}_oped" postfix has been appended to projects utilizing the OPED core.
• Reference Router
  • Reference_router project is under the testing phase and requires some SW update. We are working on it and planning for its release shortly.

This is the fifth release in the series of releases for the NetFPGA-10G beta community. It has the following new features:

• Reference Switch
  • Learning switch with TCAM (doesn't support full learning at 40G line rate for small packets, i.e. 64KB)
• Reference Switch Lite
  • Learning switch with Registers (40G line rate)
• Ported IPv4 Router
  • 10G IPv4 router using the NetFPGA 1G pipeline
• SCONE
  • Port of SCONE for the 10G router designs
• Router Kit
  • Port of Router Kit for 10G router designs
• Router CLI
  • Port of the CLI for 10G router Designs
• Generic Regs and Tables in HW
  • Register and table access using generic implementation
• NetFPGA-10G patch for XAPP852
  • RLDRAM II regression testing
• DRAM memory-mapped interface
  • AXI4 to RLDRAM II for data/instruction memory
• ARP Reply
  • AXI implementation of ARP reply with example project
• Encap/Decap
  • AXI implementation of Encap/Decap with example project and GUI

Few of the limitations that still persist are:

• FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

This is the forth release in the series of releases for the NetFPGA-10G beta community. It includes following new features:

• Reference 10G Learning CAM Switch
• Simple 10G Switch

Few of the limitations that still persist are:

• FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

This is yet another release in the series of releases for the NetFPGA-10G beta community. It provides following new features:

• OpenFlow Switch v1.0
• Register System (based on EDK workflow)
• SRAM FIFO
• Official support for Xilinx 13.4 suite

Few of the limitations that still persist are:

• FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

This is the second one in the series of releases for the NetFPGA-10G beta community. It contains following new features:

• Faster and smaller implementation of PCIe DMA Egine and Device Driver.
• Mechanics for porting NetFPGA-1G reference pipeline to the 10G platform.
• Improved R/W timing for Flash ICs. Now takes around 5 mins to program each flash.

Few of the limitations that still persist are:

• The nf10_configure utility will enter an indefinite held state if the NF10 driver is not installed.
• FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

• Input Arbiter - a dead lock condition occurs for AXI Stream between two modules [resolved]

This is the first release published after the NetFPGA-10G has transition into beta. Contains all the features of its predecessors and is now available to a wider community.

Isle of Man is another early release to the NetFPGA-10G alpha community. It contains a new feature of flash configuration. The projects are fully functional and tested, but there are few additional limitations listed below:

• Programming each Flash IC takes around 30 mins.
• The nf10_configure utility will enter an indefinite held state if the NF10 driver is not installed.
• FPGA only boots from flash if the written image (bitstream) is created using start-up clock (CCLK) during the bitgen process. In EDK, this process is hidden but you can verify this in the /hw/implementation/bitgen.ut file. The '-g StartUpClk:' option should be set to CCLK for proper working.

The golden images (bitstreams) will not be present in the later releases. They will be provided as a separate link to reduce the overall size of the release.

Skellig is an early release to the NetFPGA-10G alpha community. The designs in this projects are fully functional and tested, however we would like to point out the following issues:

• The reference NIC in 1G and 10G designs operate reliably however with a low throughput. Please check the following page for more details: NIC's Benchmark
• When running the system level simulation (make sim) for the reference_nic, we currently encounter a potential bug with isim which corrupts the outputs in the log file: nf10_oped_0_log.axi. If needed, use Modelsim until this bug is resolved.
• Flash configuration is not contained in this release.